公开(公告)号：US20250150923A1

公开(公告)日：2025-05-08

申请号：US18890141

申请日：2024-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangsoo KWON ,  Jonggun MOON ,  Seungjin CHOI ,  Yoojin CHOI ,  Jinho KIM ,  Woongjae HAN

IPC: H04W36/32 ,  H04B17/318 ,  H04W24/08 ,  H04W76/19

Abstract: A user equipment (UE) supporting a first radio access technology (RAT) network and a second RAT network, the UE includes processing circuitry configured to monitor whether a position of the UE has changed from a first position to obtain a monitoring result, a network connected to the UE switching from the first RAT network to the second RAT network based on the UE moving to the first position, and perform a re-connection operation to the first RAT network based on the monitoring result.

公开(公告)号：US20230170921A1

公开(公告)日：2023-06-01

申请号：US18058388

申请日：2022-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoochang EUN ,  Woongjae HAN

IPC: H03M13/11

CPC classification number: H03M13/1131 ,  H03M13/1148

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

公开(公告)号：US20250119161A1

公开(公告)日：2025-04-10

申请号：US18982129

申请日：2024-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoochang EUN ,  Woongjae HAN

IPC: H03M13/11 ,  H04L1/00

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.