公开(公告)号：US10311946B2

公开(公告)日：2019-06-04

申请号：US15221875

申请日：2016-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Wool Jeong ,  Woo-Jin Rim ,  Tae-Joong Song ,  Seong-Ook Jung ,  Gyu-Hong Kim

IPC: G11C7/18 ,  G11C11/419 ,  G11C11/4091

Abstract: The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.

公开(公告)号：US09940998B2

公开(公告)日：2018-04-10

申请号：US15469037

申请日：2017-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hoon Jung ,  Sung-Hyun Park ,  Woo-Jin Rim

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.

公开(公告)号：US09324384B2

公开(公告)日：2016-04-26

申请号：US14504596

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Joong Song ,  Sung-Hyun Park ,  Woo-Jin Rim ,  Gi-Young Yang

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/419

Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Abstract translation: 在感测放大器中，开关晶体管被配置为响应于感测使能信号而将接地电压施加到接地节点。 第一检测电路被配置为基于位线的模式信号和电压将第一检测信号输出到第一检测节点。 第二检测电路被配置为基于互补位线的电压将第二检测信号输出到第二检测节点。 锁存电路连接到电源电压，第一检测节点和第二检测节点，并且被配置为分别基于第一检测来通过锁存节点和互补锁存器节点输出第一放大信号和第二放大信号 信号和第二检测信号。