公开(公告)号：US10860321B2

公开(公告)日：2020-12-08

申请号：US16205297

申请日：2018-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwee Soo Kim ,  Hyuk Min Kwon ,  Won Jin Kim

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/82

Abstract: An electronic device including a memory; and a processor configured to generate an instruction code based on a same opcode when the same opcode is used in one or more slots defined in the memory upon application compiling.

公开(公告)号：US20190179670A1

公开(公告)日：2019-06-13

申请号：US16205727

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Jin Kim ,  Keong Ho Lee ,  Hyuk Min Kwon ,  Rakie Kim

IPC: G06F9/48 ,  G06F9/50

Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.

公开(公告)号：US11422852B2

公开(公告)日：2022-08-23

申请号：US16205727

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Jin Kim ,  Keong Ho Lee ,  Hyuk Min Kwon ,  Rakie Kim

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.