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1.发明申请公开(公告)号：US20190179670A1
公开(公告)日：2019-06-13
申请号：US16205727
申请日：2018-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Won Jin Kim , Keong Ho Lee , Hyuk Min Kwon , Rakie Kim
Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.
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公开(公告)号：US20150019196A1
公开(公告)日：2015-01-15
申请号：US14376612
申请日：2013-01-30
Applicant: Samsung Electronics Co., Ltd
Inventor： Hyun Woo Sim , Hyuk Min Kwon , Seung Wook Lee , Han Su Cho
CPC classification number: G06F9/3001 , G06F9/30181 , G06F9/3889 , G06F9/3897 , G06F9/52 , G06F17/5009 , G06F17/5022 , G06F17/5045 , G06F2217/68
Abstract: In order to achieve tasks, according to an embodiment of the present invention, an arithmetic unit including one or more ASIPs includes two or more processors, and an execution unit that is connected to the two or more processors and executes instructions received from the processors. According to an embodiment of the present invention, it is possible to provide a low-power, high-integration, high-performance arithmetic unit through resource sharing using the arithmetic unit including the one or more ASIPs, and it is possible to provide a method of designing an arithmetic unit that may be applied to a specific application.
Abstract translation: 为了实现任务，根据本发明的实施例，包括一个或多个ASIP的算术单元包括两个或更多个处理器，以及连接到两个或更多个处理器并执行从处理器接收的指令的执行单元。 根据本发明的实施例，可以通过使用包括一个或多个ASIP的算术单元通过资源共享来提供低功率，高集成度的高性能算术单元，并且可以提供一种方法 设计可应用于特定应用的算术单元。
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3.发明授权公开(公告)号：US11422852B2
公开(公告)日：2022-08-23
申请号：US16205727
申请日：2018-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Won Jin Kim , Keong Ho Lee , Hyuk Min Kwon , Rakie Kim
Abstract: A processor includes a plurality of cores configured to perform operations independently, a memory, and a control circuit electrically connected to the plurality of cores and the memory. The control circuit is configured to acquire one or more instructions associated with a task, store data corresponding to the task based on the one or more instructions, transmit the instructions to the at least some cores, check one or more cores that have responded to the instructions among the at least some cores, prevent the task from being allocated to the cores except for one core if the task is allocated to the one core, and allocate the task to one of the cores, the allocation of the task including changing state information associated with the allocation and setting other cores not allocated the task among the plurality of cores not to access the data corresponding to the task.
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公开(公告)号：US10860321B2
公开(公告)日：2020-12-08
申请号：US16205297
申请日：2018-11-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hwee Soo Kim , Hyuk Min Kwon , Won Jin Kim
Abstract: An electronic device including a memory; and a processor configured to generate an instruction code based on a same opcode when the same opcode is used in one or more slots defined in the memory upon application compiling.
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