公开(公告)号：US20170344307A1

公开(公告)日：2017-11-30

申请号：US15405227

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges SHAHIDI ,  Manu AWASTHI ,  Tameesh SURI ,  Vijay BALAKRISHNAN

IPC: G06F3/06

Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

公开(公告)号：US20200278805A1

公开(公告)日：2020-09-03

申请号：US16875986

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges SHAHIDI ,  Manu AWASTHI ,  Tameesh SURI ,  Vijay BALAKRISHNAN

IPC: G06F3/06

Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

公开(公告)号：US20170212708A1

公开(公告)日：2017-07-27

申请号：US15133205

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUHAS ,  Ashwini BATRAHALLI ,  Tameesh SURI

IPC: G06F3/06 ,  H04L29/08

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0679 ,  H04L67/1097

Abstract: A Solid State Drive (SSD) (110) is disclosed. The SSD (110) may include storage (218) for data, and reception circuitry (203) to receive various instructions and data. The reception circuitry (203) may receive an instruction (257) from a host machine (105) to perform garbage collection, along with a selected P/E strategy (260). The SSD (110) may include garbage collection logic (209) to perform garbage collection, possibly with a delayed Program operation if an adaptive P/E strategy (1110) is selected. The SSD (110) may also include a mapping table (221) that may identify which pages were not Programmed before victim blocks (233, 236) were erased, and therefore require replication during a delayed Program operation.

公开(公告)号：US20170344487A1

公开(公告)日：2017-11-30

申请号：US15217964

申请日：2016-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges SHAHIDI ,  Tameesh SURI ,  Manu AWASTHI ,  Vijay BALAKRISHNAN

IPC: G06F12/10

Abstract: According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

公开(公告)号：US20160094638A1

公开(公告)日：2016-03-31

申请号：US14595172

申请日：2015-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tameesh SURI ,  Manu AWASTHI

IPC: H04L29/08

CPC classification number: H04L67/104 ,  H04L47/193 ,  H04L67/2842 ,  H04L69/321

Abstract: Inventive aspects include a high bandwidth peer-to-peer switched key-value system, method, and section. The system can include a high bandwidth switch, multiple network interface cards communicatively coupled to the switch, one or more key-value caches to store a plurality of key-values, and one or more memory controllers communicatively coupled to the key-value caches and to the network interface cards. The memory controllers can include a key-value peer-to-peer logic section that can coordinate peer-to-peer communication between the memory controllers and the multiple network interface cards through the switch. The system can further include multiple transmission control protocol (TCP) offload engines that are each communicatively coupled to a corresponding one of the network interface cards. Each of the TCP offload engines can include a packet peer-to-peer logic section that can coordinate the peer-to-peer communication between the memory controllers and the network interface cards through the switch.

Abstract translation: 发明方面包括高带宽对等交换键值系统，方法和部分。 系统可以包括高带宽交换机，通信地耦合到交换机的多个网络接口卡，用于存储多个键值的一个或多个键值高速缓存以及通信地耦合到键值高速缓存的一个或多个存储器控制器，以及 到网络接口卡。 存储器控制器可以包括键值对等逻辑部分，其可以通过交换机来协调存储器控制器和多个网络接口卡之间的对等通信。 该系统还可以包括多个传输控制协议（TCP）卸载引擎，它们通信地耦合到相应的一个网络接口卡。 每个TCP卸载引擎可以包括分组对等逻辑部分，其可以通过交换机协调存储器控制器和网络接口卡之间的对等通信。