公开(公告)号：US20150318350A1

公开(公告)日：2015-11-05

申请号：US14750027

申请日：2015-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US09496336B2

公开(公告)日：2016-11-15

申请号：US14750027

申请日：2015-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US09966267B2

公开(公告)日：2018-05-08

申请号：US15292884

申请日：2016-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/423 ,  H01L27/108

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.