公开(公告)号：US20220269306A1

公开(公告)日：2022-08-25

申请号：US17559255

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Ahn ,  Sungcheol Park ,  Kiseok Bae

IPC: G06F1/12 ,  H03K3/037 ,  H03K5/01 ,  H03K19/20 ,  G06F1/06

Abstract: Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

公开(公告)号：US11698659B2

公开(公告)日：2023-07-11

申请号：US17559255

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Ahn ,  Sungcheol Park ,  Kiseok Bae

IPC: H03K3/00 ,  G06F1/12 ,  H03K3/037 ,  H03K19/20 ,  G06F1/06 ,  H03K5/01 ,  H03K5/00

CPC classification number: G06F1/12 ,  G06F1/06 ,  H03K3/037 ,  H03K5/01 ,  H03K19/20 ,  H03K2005/00013

Abstract: Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.