公开(公告)号：US20180342462A1

公开(公告)日：2018-11-29

申请号：US15815083

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Subhash KUCHANURI ,  Sidharth RASTOGI ,  Ranjan RAJEEV ,  Chul-hong PARK ,  Jae-seok YANG

IPC: H01L23/544 ,  H01L23/485 ,  G06F17/50 ,  H03K19/173

Abstract: An integrated circuit device includes: a pair of reference conductive lines arranged in parallel in a first direction in a first version logic cell and a pair of swap conductive lines arranged in parallel in a second version logic cell, wherein one reference conductive line and one swap conductive line in different wiring tracks of the pair of reference conductive lines and the pair of swap conductive lines have the same planar shape and the same length, and extend to intersect a cell boundary between the first version logic cell and the second version logic cell.

公开(公告)号：US20180102364A1

公开(公告)日：2018-04-12

申请号：US15603577

申请日：2017-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Raheel AZMAT ,  Pan-jae PARK ,  Chul-hong PARK ,  Jae-seok YANG ,  Kwan-young CHUN

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/092 ,  H01L21/76 ,  H01L21/76895 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/785 ,  H01L2027/11829

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

公开(公告)号：US20190326285A1

公开(公告)日：2019-10-24

申请号：US16453645

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Raheel AZMAT ,  Pan-jae PARK ,  Chul-hong PARK ,  Jae-seok YANG ,  Kwan-young CHUN

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/49 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/76

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

公开(公告)号：US20180157781A1

公开(公告)日：2018-06-07

申请号：US15701971

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Chul-Hong PARK ,  Jae-Seok YANG

IPC: G06F17/50 ,  H01L21/768 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.