Abstract:
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
Abstract:
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.