公开(公告)号：US12009404B2

公开(公告)日：2024-06-11

申请号：US17686504

申请日：2022-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78696

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US11296204B2

公开(公告)日：2022-04-05

申请号：US16418705

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US10361310B2

公开(公告)日：2019-07-23

申请号：US15463187

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/41 ,  H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US20240153815A1

公开(公告)日：2024-05-09

申请号：US18456561

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhoon Choi ,  Seungseok Ha ,  Seokmyeong Kang ,  Seowoo Nam

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/76819 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of manufacturing a semiconductor device includes forming conductive patterns on which stopper layers are formed, respectively, on a substrate including a first region having a first pattern density and a second region having a second pattern density lower than the first pattern density, forming a first interlayer insulating layer on the conductive patterns, exposing at least a portion of the first interlayer insulating layer on the first region and forming a photoresist pattern on the second region, etching at least a portion of the first interlayer insulating layer on the first region, performing first polishing to expose upper surfaces of ones of the stopper layers on the first region, etching the ones of the stopper layers on the first region, forming a second interlayer insulating layer on the conductive patterns, and performing second polishing to expose upper surfaces of ones of the conductive patterns on the first region.

公开(公告)号：US10804403B2

公开(公告)日：2020-10-13

申请号：US16437056

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.