公开(公告)号：US20230134878A1

公开(公告)日：2023-05-04

申请号：US17842878

申请日：2022-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon Kim ,  Kanamori Kohji ,  Jeehoon Han

IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a substrate, and a stack structure on the substrate. The stack structure includes first blocks that extend in a first direction and are arranged in a second direction intersecting the first direction, and a second block that is between the first blocks; separation structures that extend in the first direction and are arranged in the second direction between the first blocks and between the first and second blocks; vertical channel structures that penetrate the first blocks and contact the substrate; and through-via structures that penetrate the second block and the substrate. A width of each of the first blocks in the second direction is equal to a width of the second block in the second direction.

公开(公告)号：US12207468B2

公开(公告)日：2025-01-21

申请号：US17681247

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon Kim ,  Sang Hun Chun ,  Jee Hoon Han

IPC: H01L21/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a cell unit including a stack structure and a channel structure penetrating through the stack structure, the stack structure including at least one string selection gate and a plurality of cell gates, cell separation structures separating the cell unit in a first direction, and gate cutting structures defining regions within the cell unit between adjacent cell separation structures. The cell unit includes a first region defined between a first cell separation structure and a first gate cutting structure and a second region defined between the first gate cutting structure and a second gate cutting structure. A ratio of a region of the at least one string selection gate that is occupied by a conductive material in the second region is greater than a ratio of a region of at least one cell gate that is occupied by the conductive material in the second region.

公开(公告)号：US20240074192A1

公开(公告)日：2024-02-29

申请号：US18202019

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yoon Kim ,  Byoung Jae Park ,  Jae-Hwang Sim ,  Jongseon Ahn ,  Young-Ho Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06524

Abstract: A three-dimensional semiconductor device includes: a source structure including a cell region and an extension region; a gate stacking structure disposed on the source structure, the gate stacking structure including insulating patterns and conductive patterns, which are alternately stacked on each other; an insulating structure disposed on the gate stacking structure, the insulating structure including a plurality of insulating layers; a memory channel structure penetrating the gate stacking structure and electrically connected to the cell region; a separation structure penetrating the gate stacking structure and extending from the cell region to the extension region; and a penetration plug penetrating the gate stacking structure and the extension region, wherein the penetration plug includes: a first plug portion penetrating the gate stacking structure; and a second plug portion on the first plug portion, wherein the separation structure includes: a first separation portion penetrating the gate stacking structure; and a second separation portion on the first separation portion, and wherein a top surface of the first plug portion and a top surface of the first separation portion are at a substantially same level.