公开(公告)号：US20220368513A1

公开(公告)日：2022-11-17

申请号：US17586182

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Min Lee ,  Jae Hong Jung ,  Seung Jin Kim ,  Seung Hyun Oh

IPC: H04L7/00 ,  H04L7/033

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

公开(公告)号：US11018685B2

公开(公告)日：2021-05-25

申请号：US15931729

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Yong Lim ,  Seung Hyun Oh ,  Jae Hoon Lee

IPC: H03M1/38 ,  H03M1/46 ,  H03K5/24 ,  H03M1/00 ,  H03M1/12 ,  H03M1/06 ,  H03M1/10

Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

公开(公告)号：US11728961B2

公开(公告)日：2023-08-15

申请号：US17586182

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Min Lee ,  Jae Hong Jung ,  Seung Jin Kim ,  Seung Hyun Oh

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0037 ,  H04L7/033

Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

公开(公告)号：US20210091782A1

公开(公告)日：2021-03-25

申请号：US15931729

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Yong Lim ,  Seung Hyun Oh ,  Jae Hoon Lee

IPC: H03M1/46 ,  H03K5/24

Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

公开(公告)号：US10359799B2

公开(公告)日：2019-07-23

申请号：US15914095

申请日：2018-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Jang ,  Seung Hyun Oh ,  Jong Woo Lee

IPC: G05F3/16 ,  H03K17/567

Abstract: A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.

公开(公告)号：US10951203B1

公开(公告)日：2021-03-16

申请号：US16842051

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jin Kim ,  Wan Kim ,  Seung Hyun Oh ,  Byung Ki Han

IPC: H03K5/22 ,  H03K5/24 ,  H03B5/12 ,  H03B5/04

Abstract: A semiconductor device and a method for controlling amplitude of signal in the semiconductor device are provided. The semiconductor device comprises a signal generator configured to output a sinewave, a comparator configured to compare a magnitude of the sinewave with a magnitude of a reference signal at a first timing corresponding to a timing control signal and to output a comparison result, and a control signal adjustor configured to adjust one of the current control signal and a timing control signal depending on the comparison result of the comparator.