公开(公告)号：US20230170216A1

公开(公告)日：2023-06-01

申请号：US17870309

申请日：2022-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjoo AN ,  Seran OH ,  Yeonuk KIM

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0332 ,  H01L21/022 ,  H01L21/02115

Abstract: A hard mask film for use in a process for manufacture of a semiconductor device, comprises a first graphene layer; a first amorphous carbon layer formed on the first graphene layer; a second graphene layer formed on the first amorphous carbon layer; and a second amorphous carbon layer formed on the second graphene layer.

公开(公告)号：US20250132198A1

公开(公告)日：2025-04-24

申请号：US18669981

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunho KANG ,  Minsik KIM ,  Yeonuk KIM ,  Seran OH ,  Byounghoon LEE ,  Jangeun LEE

IPC: H01L21/768 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.

公开(公告)号：US20230102650A1

公开(公告)日：2023-03-30

申请号：US17954960

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geuno JEONG ,  Janghee LEE ,  Sungjoo AN ,  Seran OH

IPC: H01L21/02 ,  H01L21/687 ,  C23C16/458 ,  C23C16/02 ,  C23C16/455 ,  C23C16/46 ,  C23C16/26

Abstract: A substrate processing apparatus includes: configured to support a plurality of substrates; a chamber sidewall surrounding at least a side surface of the substrate support; and an upper plate including a plurality of plate portions on the substrate support and spaced apart from the substrate support. The plurality of plate portions and the substrate support collectively at least partially define a plurality of process regions between the plurality of plate portions and the substrate support and a separation between at least two process regions of the plurality of process regions. The plurality of process regions include a pretreatment process region between the pretreatment process plate portion and the substrate support and having a first height, and a deposition process region between the deposition process plate portion and the substrate support and having a second height, greater than the first height.