公开(公告)号：US20210020835A1

公开(公告)日：2021-01-21

申请号：US17060884

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun LEE ,  Seongjun PARK ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Kibum KIM ,  Sanghun LEE ,  Yunho KANG

IPC: H01L45/00 ,  H01L21/768 ,  G11C13/00

Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode separated from the first electrode, a resistive-change material layer provided between the first electrode and the second electrode and configured to store information due to a resistance change caused by an electrical signal applied through the first electrode and the second electrode, and a diffusion prevention layer provided between the first electrode and the resistive-change material layer and/or between the second electrode and the resistive-change material layer and including a two-dimensional (2D) material having a monolayer thickness of about 0.35 nm or less.

公开(公告)号：US20250132198A1

公开(公告)日：2025-04-24

申请号：US18669981

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunho KANG ,  Minsik KIM ,  Yeonuk KIM ,  Seran OH ,  Byounghoon LEE ,  Jangeun LEE

IPC: H01L21/768 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.