公开(公告)号：US10943939B2

公开(公告)日：2021-03-09

申请号：US16271917

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Chang-Rok Moon ,  Seung-Hun Shin ,  Seong-Ho Oh ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L29/40 ,  H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

公开(公告)号：US20150221695A1

公开(公告)日：2015-08-06

申请号：US14561854

申请日：2014-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Chang-Rok Moon ,  Seung-Hun Shin ,  Seong-Ho Oh ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L27/146 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

Abstract translation: 半导体器件包括下部器件和设置在下部器件上的上部器件。 下部器件包括下部衬底，设置在下部衬底上的下部插头焊盘以及下部插头焊盘上的下部层间电介质层。 上部器件包括上部衬底，上部衬底的下部中的蚀刻延迟结构，设置在上部衬底的底部表面上的上部焊盘，位于上部焊盘上的上层间绝缘层，以及通孔 插头被配置为穿透上基板并接触上插头垫和下插头垫。 通孔插头包括与上插头焊盘和第一蚀刻延迟结构接触的第一部分，以及与下插头焊盘接触的第二部分。

公开(公告)号：US10229949B2

公开(公告)日：2019-03-12

申请号：US15625387

申请日：2017-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Chang-Rok Moon ,  Seung-Hun Shin ,  Seong-Ho Oh ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L29/40 ,  H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

公开(公告)号：US09728572B2

公开(公告)日：2017-08-08

申请号：US14561854

申请日：2014-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Jun Park ,  Chang-Rok Moon ,  Seung-Hun Shin ,  Seong-Ho Oh ,  Tae-Seok Oh ,  June-Taeg Lee

IPC: H01L29/40 ,  H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.