公开(公告)号：US09899416B2

公开(公告)日：2018-02-20

申请号：US15403307

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Soon Kim ,  Hyun Ji Kim ,  Jeong Yun Lee ,  Gi Gwan Park ,  Sang Duk Park ,  Young Mook Oh ,  Yong Seok Lee

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7853

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

公开(公告)号：US20240072140A1

公开(公告)日：2024-02-29

申请号：US18502324

申请日：2023-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Hyuk Lee ,  Jong Chul Park ,  Sang Duk Park ,  Hong Sik Shin ,  Do Haing Lee

IPC: H01L29/417 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

公开(公告)号：US11848364B2

公开(公告)日：2023-12-19

申请号：US17318079

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Hyuk Lee ,  Jong Chul Park ,  Sang Duk Park ,  Hong Sik Shin ,  Do Haing Lee

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L23/485 ,  H01L23/528

CPC classification number: H01L29/41791 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

公开(公告)号：US20220109055A1

公开(公告)日：2022-04-07

申请号：US17318079

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Hyuk Lee ,  Jong Chul Park ,  Sang Duk Park ,  Hong Sik Shin ,  Do Haing Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

公开(公告)号：US10224343B2

公开(公告)日：2019-03-05

申请号：US15869599

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Soon Kim ,  Hyun Ji Kim ,  Jeong Yun Lee ,  Gi Gwan Park ,  Sang Duk Park ,  Young Mook Oh ,  Yong Seok Lee

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/78

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.