公开(公告)号：US20250017013A1

公开(公告)日：2025-01-09

申请号：US18887445

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20230309307A1

公开(公告)日：2023-09-28

申请号：US18080916

申请日：2022-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Miram KWON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction, a stack structure including electrode layers and insulating layers, which are alternately stacked on the substrate, the electrode layers including upper electrode layers, a first insulating line pattern on the separation region to penetrate the upper electrode layers and extend in a second direction crossing the first direction, second and third insulating line patterns on the separation region to penetrate the first insulating line pattern and the stack structure and to extend in the second direction to divide the stack structure into first and second sub-stack structures, and a remaining stack structure between the second and third insulating line patterns and spaced apart from the first and second sub-stack structures.

公开(公告)号：US20230084557A1

公开(公告)日：2023-03-16

申请号：US17869909

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having cell and connection regions, and a stack structure having dielectric layers and electrodes that are vertically and alternately stacked on the substrate. The stack structure includes a first pad part, a first fence part, a second pad part, and a second fence part that are sequentially arranged along a first direction. Each of the first and second pad parts has a first stepwise structure formed along the first direction and a second stepwise structure formed along a second direction that intersects the first direction, and each of the first and second fence parts includes dummy electrodes at the same levels as the electrodes and spaced apart from the electrodes. Sidewalls of the electrodes that define second stepwise structure of the second part are offset from sidewalls of the dummy electrodes that define second dummy stepwise structure of the first pad part.

公开(公告)号：US20220392916A1

公开(公告)日：2022-12-08

申请号：US17679268

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/06

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20220157831A1

公开(公告)日：2022-05-19

申请号：US17378317

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Younghwan SON ,  Miram KWON ,  Junyong PARK ,  Jiho LEE

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer.