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公开(公告)号：US20180205886A1
公开(公告)日：2018-07-19
申请号：US15684276
申请日：2017-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seon-ju Lee , Dae-hwa Paik , Seung-hyun Lim , Kyoung-min Koh , Min-ho Kwon , Jin-woo Kim
CPC classification number: H04N5/23245 , H04N5/343 , H04N5/345 , H04N5/3452 , H04N5/3698 , H04N5/378
Abstract: In some embodiments, a method of operating an image sensor supporting a low speed mode and a high speed mode includes: outputting a first set of output signals from a first pixel group to a first output line group by enabling, during a first period of the low speed mode, a first load circuit group connected to the first set of output signals; outputting a second set of output signals from a second pixel group to a second output line group by enabling, during a second period of the low speed mode different from the first period, a second load circuit group connected to the second set of output signals; and disabling the second load circuit group during at least a part of the first period.
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公开(公告)号：US11140346B2
公开(公告)日：2021-10-05
申请号：US15718598
申请日：2017-09-28
Applicant: Samsung Electronics Co., Ltd. , Industry-Academic Cooperation Foundation, Yonsei University
Inventor： Youngcheol Chae , Sang-hyun Cho , Min-ho Kwon , Seung-hyun Lim , Woo-jin Jo
Abstract: An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.
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公开(公告)号：US20180109747A1
公开(公告)日：2018-04-19
申请号：US15718598
申请日：2017-09-28
Applicant: Samsung Electronics Co., Ltd. , Industry-Academic Cooperation Foundation, Yonsei University
Inventor： Youngcheol Chae , Sang-hyun Cho , Min-ho Kwon , Seung-hyun Lim , Woo-jin Jo
CPC classification number: H04N5/378 , H03M1/124 , H03M1/162 , H03M1/361 , H03M1/38 , H03M1/56 , H03M3/46 , H03M3/494 , H04N5/37455
Abstract: An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.
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