MEMORY DEVICE AND REFRESH CONTROLLING METHOD THEREOF

    公开(公告)号:US20250006242A1

    公开(公告)日:2025-01-02

    申请号:US18522252

    申请日:2023-11-29

    Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells disposed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts for the plurality of rows, and a refresh controller configured to determine a refresh address based on the stored row addresses and a refresh command being received, and change a refresh period for a target row based on the refresh address being associated with a previously performed refresh for the target row and the access count for a row corresponding to the target row being reached a threshold value.

    MEMORY DEVICE INCLUDING ADDRESS TABLE AND OPERATING METHOD FOR MEMORY CONTROLLER

    公开(公告)号:US20230350809A1

    公开(公告)日:2023-11-02

    申请号:US18140974

    申请日:2023-04-28

    CPC classification number: G06F12/10

    Abstract: A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

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