公开(公告)号：US20230350809A1

公开(公告)日：2023-11-02

申请号：US18140974

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHINAM KIM ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DOHAN KIM ,  BYEONGNOH KIM ,  BOBAE KIM ,  CHANGMIN LEE ,  KYEONGJIN CHO ,  INSU CHOI

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

公开(公告)号：US20250044941A1

公开(公告)日：2025-02-06

申请号：US18441475

申请日：2024-02-14

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： CHINAM KIM ,  DO-HAN KIM ,  CHANGMIN LEE

IPC: G06F3/06

Abstract: A memory device with a computation function includes a first cell array including first memory cells connected to word lines, a second cell array including second memory cells connected to the word lines, a first bit line sense amplifier that sense first voltages of first bit lines connected to the first memory cells, a second bit line sense amplifier that senses second voltages of second bit lines connected to the second memory cells, a first column selection circuit that outputs a first output signal among the first voltages based on a first column compute selection signal, a second column selection circuit that outputs a second output signal among the second voltages based on a second column compute selection signal different from the first column compute selection signal, and a column compute control circuit that generates the first column compute selection signal and the second column compute selection signal.