公开(公告)号：US20210074719A1

公开(公告)日：2021-03-11

申请号：US16853838

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

公开(公告)号：US20230253329A1

公开(公告)日：2023-08-10

申请号：US18135766

申请日：2023-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Min HWANG ,  Jong Soo KIM ,  Ju-Young LIM ,  Won Seok CHO

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L24/08 ,  H01L25/18 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

公开(公告)号：US20220223525A1

公开(公告)日：2022-07-14

申请号：US17488727

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Min HWANG ,  Jong Soo KIM ,  Ju-Young LIM ,  Won Seok CHO

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

公开(公告)号：US20220238552A1

公开(公告)日：2022-07-28

申请号：US17718676

申请日：2022-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11529

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

公开(公告)号：US20210399008A1

公开(公告)日：2021-12-23

申请号：US17154159

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Young LIM ,  Jongsoo KIM ,  Jesuk MOON ,  Dongwoo KIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.