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    WIRING STRUCTURE AND METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE
    1.
    发明申请
    WIRING STRUCTURE AND METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE 有权
    导线结构及其形成方法，以及包括布线结构的半导体器件

    公开(公告)号：US20160379891A1

    公开(公告)日：2016-12-29

    申请号：US15187901

    申请日：2016-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JIN-HYEUNG PARK ,  Yeon-Joo Kim ,  In-Hwan Kim ,  Jun-Jung Kim ,  Kyoung-Pil Park ,  Jeong-Hoon Ahn ,  Sang-Chul Lee ,  Joon-Nyung Lee ,  Hyo-Seon Lee

    IPC: H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/823475 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

    Abstract: In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.

    Abstract translation: 在形成布线结构的方法中，形成具有第一开口的第一掩模，第一开口包括沿第二方向延伸的第一部分和沿第一方向延伸的第二部分。 设计了包括与第一开口的第一部分重叠的第二开口和与第一开口的第二部分重叠的第三开口的第二掩模。 通过扩大第二开口将第二掩模制造成包括第四开口。 第四开口与第一开口的第一和第二部分之间的边界重叠。 使用第一和第二掩模蚀刻绝缘中间层，以形成对应于第四和第三开口的第一和第二通孔以及对应于第一开口的沟槽。 形成第一和第二通孔和布线以填充第一和第二通孔和沟槽。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11469174B2

    公开(公告)日：2022-10-11

    申请号：US17231915

    申请日：2021-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon-Nyung Lee ,  Jeong Hoon Ahn

    IPC: H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11257754B2

    公开(公告)日：2022-02-22

    申请号：US16550189

    申请日：2019-08-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon-Nyung Lee ,  Jeong Hoon Ahn

    IPC: H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10424513B2

    公开(公告)日：2019-09-24

    申请号：US16005886

    申请日：2018-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Il Park ,  Jeong Hoon Ahn ,  Joon-Nyung Lee

    IPC: H01L21/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58

    Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

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