公开(公告)号：US11244632B2

公开(公告)日：2022-02-08

申请号：US17026639

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeeyeon Eom ,  Soonchan Kwon ,  Kyungjik Min ,  Yeongshin Jang ,  Jeonghoon Choi ,  Siwoo Kim ,  Jaeyoun Lee

IPC: G09G3/00 ,  G09G3/3275 ,  G09G3/3258

Abstract: A display driving integrated circuit includes a timing controller, a first source driver including a first inverting input, a first non-inverting input, and a first output, a second source driver including a second inverting input, a second non-inverting input, and a second output, and a switching circuit connected with the display panel through a first and second pads. Under control of the timing controller, the switching circuit performs one of a first switching operation of connecting the first inverting input and the first output with the first pad, connecting the second inverting input and the second output with the second pad, and applying first and second decoding voltages to the non-inverting inputs, respectively; and a second switching operation of applying a sensing reference voltage to the non-inverting inputs, and connecting the output terminals with an output node, and connecting the inverting inputs with one pad.

公开(公告)号：US20240152461A1

公开(公告)日：2024-05-09

申请号：US18350148

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Woo Ro ,  Hyoseong Choi ,  Jiwon Lee ,  Jeonghoon Choi

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

公开(公告)号：US12218785B2

公开(公告)日：2025-02-04

申请号：US18033670

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Cho ,  Jeonghoon Choi

IPC: H04L25/03 ,  H04L5/00 ,  H04L27/00 ,  H04L27/26

Abstract: Provided are a discrete Fourier transform (DFT)-spread orthogonal frequency division multiplexing (OFDM) transmitter and transmission method, and a DFT-spread OFDM receiver and reception method which may receive signals transmitted thereby, in which a constellation rotation angle and a frequency domain spectrum shaping vector are designed such that a PAPR may be easily traded off with frequency efficiency even without inter-symbol interference. The DFT-spread OFDM transmitter includes a constellation rotation unit constellation-rotating a symbol vector including M pulse amplitude modulation (PAM) symbols by a constellation rotation angle to generate a constellation-rotated symbol vector, a pruned DFT-spread unit spreading the constellation-rotated symbol vector by using a pruned DFT matrix to generate a pruned DFT-spread vector, a frequency domain spectrum shaping unit performing a Hadamard product on the pruned DFT-spread vector with a shaping vector to generate a frequency domain spectrum shaped vector, and a subcarrier allocation unit allocating the frequency domain spectrum shaped vector to a subcarrier in an allocated frequency range.

公开(公告)号：US11721262B2

公开(公告)日：2023-08-08

申请号：US17745246

申请日：2022-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyeon Eom ,  Jeonghoon Choi ,  Yeongshin Jang ,  Youngbae Moon ,  Woonyoung Lee

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0413 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/08

Abstract: Provided is a display driving circuit including a plurality of source channels configured to provide data voltages to a plurality of data lines of a display panel, respectively; a dummy channel on one side of at least one of the source channels; and control logic configured to control operations of the source channels and the dummy channel, wherein, when failure of a first source channel from among the source channels is determined, the control logic is further configured to provide data voltages to data lines corresponding to the first source channel and second source channels, respectively, which are between the first source channel and the dummy channel, by using the second source channels and the dummy channel.