公开(公告)号：US20240202136A1

公开(公告)日：2024-06-20

申请号：US18502058

申请日：2023-11-05

Applicant: SAMSUNG ELECTRONICS CO.,LTD

Inventor： Jiwon Lee ,  Won Woo Ro ,  Ipoom Jeong ,  Hongju Kal ,  Gun Ko ,  Hyunwuk Lee

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: A memory management unit includes a TLB configured to cache PTEs including a mapping between a virtual and a physical frame number, and to convert a virtual address into a physical address using the cached PTEs. A page table walk request queue is configured to queue page requests corresponding to a virtual page number when a TLB miss is occurred, and one or more PTWs are configured to acquire a PTE from the main memory, and to convert the virtual page numbers into physical frame numbers using the PTE. A PTW is configured to select associated page table walk requests having the same base address of corresponding virtual page numbers, to consecutively provide cache line requests for acquiring PTEs corresponding to the associated page table walk requests, to acquire the PTEs corresponding to the associated PTE requests, and to provide the acquired PTEs to the TLB.

公开(公告)号：US11860793B2

公开(公告)日：2024-01-02

申请号：US17526391

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Won Woo Ro ,  William Jinho Song ,  Jiwon Lee

IPC: G06F12/109

CPC classification number: G06F12/109 ,  G06F2212/651 ,  G06F2212/657

Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

公开(公告)号：US12287984B2

公开(公告)日：2025-04-29

申请号：US18531094

申请日：2023-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hongju Kal ,  Won Woo Ro ,  Seokmin Lee ,  Gun Ko

IPC: G06F3/06

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

公开(公告)号：US20130254386A1

公开(公告)日：2013-09-26

申请号：US13848622

申请日：2013-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Kim ,  Sun-Mi Kim ,  Won Woo Ro ,  Changmin Lee ,  Wonseb Jeong ,  Jin-Won Kim

IPC: G06F15/173

CPC classification number: G06F15/173 ,  H04L67/322 ,  H04L69/24

Abstract: According to one embodiment, a scheduling method for load balancing in an electronic device such as a server when performing multiple transcoding operations includes performing a first transcoding operation in order to transmit at least one moving image file to a first terminal. The server receives a request from a second terminal to transmit at least one moving image file while performing the first transcoding. The server performs a second transcoding operation in order to transmit the requested moving image file to the second terminal. The server monitors output frame rates of the first transcoding operation and the second transcoding operation, to control the output frame rates.

Abstract translation: 根据一个实施例，当执行多个代码转换操作时，诸如服务器之类的电子设备中的负载平衡的调度方法包括执行第一代码转换操作，以将至少一个运动图像文件发送到第一终端。 服务器在执行第一代码转换时接收来自第二终端的请求以发送至少一个运动图像文件。 服务器执行第二代码转换操作，以便将请求的运动图像文件发送到第二终端。 服务器监视第一代码转换操作和第二代码转换操作的输出帧速率，以控制输出帧速率。

公开(公告)号：US12298901B2

公开(公告)日：2025-05-13

申请号：US18315576

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Industry—Academic Cooperation Foundation, Yonsei University

Inventor： Won Woo Ro ,  Seunghyun Jin ,  Jonghyun Lee ,  Hyunwuk Lee

IPC: G06F12/02 ,  G06F12/0875

Abstract: An apparatus and method with register sharing are provided. In one general aspect, a method of operating a processing apparatus includes determining whether there is shared data that is used by each of threads in a plurality of threads sharing a shared memory, based on an instruction that has been decoded, based on determining whether there is shared data that is used by each of the threads in the plurality of threads, determining whether an address of the shared data corresponding to each of the threads in the plurality of threads is stored in an address-to-register mapping table, based on a result of either the determining whether the address is stored in the address-to-register mapping table, mapping the address of the shared data to a shared register corresponding to the shared data, and loading the shared data based on the shared register.

公开(公告)号：US20240152461A1

公开(公告)日：2024-05-09

申请号：US18350148

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Woo Ro ,  Hyoseong Choi ,  Jiwon Lee ,  Jeonghoon Choi

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

公开(公告)号：US11582615B2

公开(公告)日：2023-02-14

申请号：US16959277

申请日：2018-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

Inventor： Seungku Han ,  Won Woo Ro ,  Byungchul Kim ,  Myungkuk Yoon ,  Hyunjin Chung ,  Youngju Lee

IPC: H04W16/18 ,  H04B17/318 ,  G06T7/62 ,  G06F30/20 ,  G06T1/20 ,  G06T15/06

Abstract: Disclosed is a 5G or pre-5G communication system for supporting a data transmission rate higher than that of a 4G communication system such as LTE. The present invention relates to a method by which a simulator analyzes a radio wave environment in a wireless communication system, and the method of the present invention comprises the steps of: allowing a simulator to receive geographic information and position information by which a transmitter and a receiver can be positioned in the geographic information; generating, by the transmitter of the simulator arranged at a random position in accordance with the position information, radio waves for at least one direction of a sphere having a fixed radius; grouping into at least one group on the basis of a traveling route of the generated radio waves; setting each group as an operation unit (Warp/Wavefront) for a graphics processing unit (GPU); and analyzing a radio wave environment by using the GPU in which the operation unit is set.

公开(公告)号：US12223444B2

公开(公告)日：2025-02-11

申请号：US17372788

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd. ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Ho Young Kim ,  Won Woo Ro ,  Sung Ji Choi

IPC: G06N5/048 ,  G06F9/48 ,  G06F9/50

Abstract: Disclosed is an accelerator and a method of operating the accelerator including determining whether any group shares weights of a first group from among groups, determining a presence of an idle processing element (PE) array, in response to no group sharing the weights of the first group, and selecting a second group having a memory time overlapping a computation time of the first group from among the groups, in response to the idle PE array being present.

公开(公告)号：US11880590B2

公开(公告)日：2024-01-23

申请号：US17837286

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hongju Kal ,  Won Woo Ro ,  Seokmin Lee ,  Gun Ko

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

公开(公告)号：US10671307B2

公开(公告)日：2020-06-02

申请号：US15869393

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-ho Lee ,  Ho-jun Shim ,  Won Woo Ro ,  Won Seob Jeong ,  Myung Kuk Yoon ,  Won Jeon

IPC: G06F3/06 ,  G06K9/00 ,  G06K9/62

Abstract: Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.