公开(公告)号：US09786624B2

公开(公告)日：2017-10-10

申请号：US15222155

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-chan Lee ,  Chang-yong Park ,  Hun Han ,  Jae-hoon Choi

IPC: H01L23/13 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A semiconductor package includes a substrate having a groove in an upper surface. A semiconductor device is mounted on the substrate to cover one portion of the groove and leaving another portion exposed.

公开(公告)号：US09761519B2

公开(公告)日：2017-09-12

申请号：US15155008

申请日：2016-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon Choi ,  Chang-yong Park ,  Dong-woo Shin

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/02 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A package substrate includes: a body layer; and a pattern layer formed on a surface of the body layer. The pattern layer includes: a wire pattern; a solder pad connected to the wire pattern; and a through hole adjacent to a boundary between the wire pattern and the solder pad and vertically penetrating the pattern layer. A semiconductor package and an electronic device are disclosed.

公开(公告)号：US20170084511A1

公开(公告)日：2017-03-23

申请号：US15222155

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-chan Lee ,  Chang-yong Park ,  Hun Han ,  Jae-hoon Choi

IPC: H01L23/29 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A semiconductor package includes a substrate having a groove in an upper surface. A semiconductor device is mounted on the substrate to cover one portion of the groove and leaving another portion exposed.