公开(公告)号：US09747224B2

公开(公告)日：2017-08-29

申请号：US14644951

申请日：2015-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tai-Song Jin ,  Jae-Un Park ,  Do-hyung Kim ,  Seung-won Lee

IPC: G06F3/00 ,  G06F13/12 ,  G06F5/00 ,  G06F13/28 ,  G06F13/00 ,  G06F13/36 ,  G06F13/10 ,  G06F1/32

CPC classification number: G06F13/102 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.

公开(公告)号：US10956159B2

公开(公告)日：2021-03-23

申请号：US14554785

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Un Park ,  Suk-Jin Kim ,  Do-Hyung Kim

IPC: G06F9/30 ,  G06F9/38

Abstract: In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced.

公开(公告)号：US09639357B2

公开(公告)日：2017-05-02

申请号：US13690079

申请日：2012-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok Kwon ,  Jae-Un Park ,  Suk-Jin Kim

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30043

Abstract: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

公开(公告)号：US09122565B2

公开(公告)日：2015-09-01

申请号：US13709542

申请日：2012-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Un Park ,  Ki-Seok Kwon ,  Suk-Jin Kim

IPC: G06F12/10 ,  G06F12/00 ,  G06F13/18 ,  G06F13/16

CPC classification number: G06F12/00 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/18

Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

Abstract translation: 提供了一种管理处理器和存储器之间的存储器访问请求的存储器控​​制器。 响应于存储器控制器接收到相同存储器区域的两个或多个存储器访问请求，存储器控制器被配置为停止存储器控制器并且顺序地处理存储器访问请求。

公开(公告)号：US09804853B2

公开(公告)日：2017-10-31

申请号：US14258640

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Un Park ,  Suk-jin Kim

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30178

Abstract: Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in the VLIW processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle; an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and an instruction converter configured to include the generated indicator code in the compressed instruction bundle.

公开(公告)号：US09330057B2

公开(公告)日：2016-05-03

申请号：US13711418

申请日：2012-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Kwan Suh ,  Suk-Jin Kim ,  Hyeong-Seok Yu ,  Ki-Seok Kwon ,  Jae-Un Park

IPC: G06F15/78 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F15/7867 ,  G06F9/3001 ,  G06F9/3867

Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

Abstract translation: 可重配置处理器包括多个微型核心和连接微型核心的外部网络。 每个微型核心包括包括第一组操作元件的第一功能单元，包括与第一组操作元件不同的第二组操作元件的第二功能单元，以及内部网络，第一功能单元 单元和第二个功能单元连接。