公开(公告)号：US11417536B2

公开(公告)日：2022-08-16

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Hee Jang ,  Seok Ho Kim ,  Hoon Joo Na ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146 ,  H01L23/00

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

公开(公告)号：US09744241B2

公开(公告)日：2017-08-29

申请号：US14242568

申请日：2014-04-01

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Hyun-Ryoung Kim ,  Jae Hyung Park ,  Hong Yeol Yoon

IPC: A61K9/00 ,  A61K47/32 ,  A61K47/36 ,  A61K9/14 ,  A61K9/19 ,  C12N15/88 ,  C12N15/11

CPC classification number: A61K47/32 ,  A61K9/146 ,  A61K9/19 ,  A61K47/36 ,  C12N15/111 ,  C12N15/88 ,  C12N2310/14 ,  C12N2320/32

Abstract: A hyaluronic acid conjugates including hyaluronic acid, a disulfide bond-containing crosslinking agent, and a cationic, amphiphilic polymer; a hyaluronic acid-nucleic acid complex in which a nucleic acid is bound to the hyaluronic acid conjugate; a composition in which the hyaluronic acid-nucleic acid complexes are crosslinked with each other; a nucleic acid delivery composition including the hyaluronic acid-nucleic acid complex; and a method of nucleic acid delivery using the hyaluronic acid-nucleic acid complex.

公开(公告)号：US11487323B2

公开(公告)日：2022-11-01

申请号：US16477492

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd

Inventor： Seung Geol Baek ,  Moon Soo Kim ,  Jae Hyung Park ,  Chi Hyun Cho ,  Yun Jang Jin ,  Ho Chul Hwang

IPC: G06F1/16 ,  B06B1/02 ,  B06B1/06 ,  G06V40/13 ,  G06F3/0484 ,  G06F3/044 ,  G01B17/02 ,  G01N29/07 ,  G01N29/28

Abstract: Disclosed is an electronic device. The electronic device according to an embodiment may include an ultrasonic sensor and a processor electrically connected to the ultrasonic sensor. The processor may be configured to obtain a noise signal at a periphery of the electronic device, via the ultrasonic sensor, to determine an attribute of a first ultrasonic signal oscillated by the ultrasonic sensor, based on the obtained noise signal, and to obtain fingerprint information based on the second ultrasonic signal obtained via the ultrasonic sensor and the determined attribute. Moreover, various embodiment found through the disclosure are possible.

公开(公告)号：US11945744B2

公开(公告)日：2024-04-02

申请号：US18134906

申请日：2023-04-14

Applicant: Samsung Engineering Co., Ltd. ,  Samsung Electronics Co., Ltd.

Inventor： Seok Hwan Hong ,  Dae Soo Park ,  Seung Joon Chung ,  Yong Xun Jin ,  Jae Hyung Park ,  Jae Hoon Choi ,  Jae Dong Hwang ,  Jong Keun Yi ,  Su Hyoung Cho ,  Kyu Won Hwang ,  June Yurl Hur ,  Je Hun Kim ,  Ji Won Chun

IPC: C02F9/00 ,  B01D61/02 ,  B01D61/14 ,  B01D61/58 ,  B01D65/02 ,  C02F1/52 ,  C02F1/56 ,  C02F1/66 ,  C02F1/00 ,  C02F1/20 ,  C02F1/44 ,  C02F1/50 ,  C02F3/12 ,  C02F3/30 ,  C02F3/34 ,  C02F5/08 ,  C02F101/14 ,  C02F101/16 ,  C02F101/30 ,  C02F103/08

CPC classification number: C02F9/00 ,  B01D61/025 ,  B01D61/145 ,  B01D61/147 ,  B01D61/58 ,  B01D65/02 ,  C02F1/5236 ,  C02F1/56 ,  C02F1/66 ,  B01D2317/025 ,  C02F2001/007 ,  C02F1/20 ,  C02F1/441 ,  C02F1/444 ,  C02F1/50 ,  C02F3/1268 ,  C02F3/30 ,  C02F3/342 ,  C02F5/08 ,  C02F2101/14 ,  C02F2101/16 ,  C02F2101/30 ,  C02F2103/08 ,  C02F2301/046 ,  C02F2303/04 ,  C02F2303/16

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

公开(公告)号：US10802643B2

公开(公告)日：2020-10-13

申请号：US15921094

申请日：2018-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyung Park ,  Seung Geol Baek ,  Chi Hyun Cho ,  Moon Soo Kim ,  Yun Jang Jin ,  Ho Chul Hwang

IPC: G06F3/041 ,  G06K9/00 ,  G06F3/044

Abstract: An electronic device is provided. The electronic device includes a display including a touch sensor and a display panel, a fingerprint sensor included in the display or disposed on a rear surface of the display, and at least one processor electrically connected with the display and the fingerprint sensor. The at least one processor controls an operation of the touch sensor or lowers a frequency of an operating signal of the touch sensor in response to a specified event, activates the fingerprint sensor, and captures a fingerprint image from the fingerprint sensor.

公开(公告)号：US20200168471A1

公开(公告)日：2020-05-28

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOO HEE JANG ,  Seok Ho Kim ,  Hoon Joo NA ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region