NEURAL NETWORK PROCESSOR USING DYADIC WEIGHT MATRIX AND OPERATION METHOD THEREOF

    公开(公告)号:US20200167637A1

    公开(公告)日:2020-05-28

    申请号:US16675709

    申请日:2019-11-06

    Abstract: An neural network (NN) processor includes an input feature map buffer configured to store an input feature matrix, a weight buffer configured to store a weight matrix trained in a form of a, a transform circuit configured to perform a Walsh-Hadamard transform on an input feature vector obtained from the input feature matrix and a weight vector included in the weight matrix to output a transformed input feature vector and a transformed weight vector, and an arithmetic circuit configured to perform an element-wise multiplication (EWM) on the transformed input feature vector and the transformed weight vector.

    METHOD AND APPARATUS FOR PROVIDING ADVANCED INDICATION FOR ePDCCH
    3.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING ADVANCED INDICATION FOR ePDCCH 有权
    用于为ePDCCH提供高级指示的方法和装置

    公开(公告)号:US20150230173A1

    公开(公告)日:2015-08-13

    申请号:US14564733

    申请日:2014-12-09

    Abstract: A method and an apparatus are provided for determining whether an enhanced physical downlink control channel (ePDCCH) transmission exists for a user equipment (UE) in a subframe. The UE receives a transmission on physical downlink control channel (PDCCH) resources of the subframe. Downlink control information (DCI) is extracted from the PDCCH resources. The DCI includes at least one bit indicating whether the ePDCCH transmission exists for the UE in the subframe. The UE determines whether the ePDCCH transmission exists using the at least one bit. Additional symbols of the subframe are buffered and decoded when the ePDCCH transmission exists.

    Abstract translation: 提供了一种用于确定在子帧中是否存在针对用户设备(UE)的增强物理下行链路控制信道(ePDCCH)传输的方法和装置。 UE在子帧的物理下行链路控制信道(PDCCH)资源上接收传输。 从PDCCH资源提取下行链路控制信息(DCI)。 DCI包括至少一个位,指示在子帧中UE是否存在ePDCCH传输。 UE确定使用至少一个比特是否存在ePDCCH传输。 当存在ePDCCH传输时,子帧的附加符号被缓冲和解码。

    SYSTEM AND METHODS FOR LOW COMPLEXITY LIST DECODING OF TURBO CODES AND CONVOLUTIONAL CODES
    5.
    发明申请
    SYSTEM AND METHODS FOR LOW COMPLEXITY LIST DECODING OF TURBO CODES AND CONVOLUTIONAL CODES 审中-公开
    系统和方法用于低复杂度列表解码的涡轮代码和转换代码

    公开(公告)号:US20150236717A1

    公开(公告)日:2015-08-20

    申请号:US14565082

    申请日:2014-12-09

    Abstract: A method and system for decoding a signal are provided. The method includes receiving a signal, where the signal includes at least one symbol; decoding the signal in stages, where each at least one symbol is decoded into at least one bit per stage, wherein a Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining the magnitudes of the LLRs; identifying K bits of the signal with the smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with the largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords, and stopping after a first candidate codeword passes the CRC.

    Abstract translation: 提供了一种用于解码信号的方法和系统。 该方法包括接收信号,其中该信号包括至少一个符号; 其中每个至少一个符号被解码成每级至少一个比特,其中为每个阶段的每个至少一个比特确定每个可能路径的对数似然比(LLR)和路径量度 ; 确定LLR的大小; 识别具有最小对应LLR幅度的信号的K位; 针对用户可定义数量的解码器级,为每个解码器级识别具有最大路径度量的L个可能路径中的每一个的K个比特; 对于L个可能路径中的每一个,执行前向和后向跟踪,以确定候选码字; 对候选码字执行循环冗余校验(CRC),并在第一候选码字通过CRC之后停止。

    SYSTEM AND METHODS FOR LOW COMPLEXITY LIST DECODING OF TURBO CODES AND CONVOLUTIONAL CODES

    公开(公告)号:US20190173497A1

    公开(公告)日:2019-06-06

    申请号:US16272653

    申请日:2019-02-11

    Abstract: A method, system, and non-transitory computer-readable recording medium of decoding a signal are provided. The method includes receiving signal to be decoded, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining magnitudes of the LLRs; identifying K bits of the signal with smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords; and stopping after a first candidate codeword passes the CRC.

    IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD FOR HIGH RESOLUTION DISPLAY, AND APPLICATION PROCESSOR INCLUDING THE SAME

    公开(公告)号:US20220068201A1

    公开(公告)日:2022-03-03

    申请号:US17215507

    申请日:2021-03-29

    Abstract: An image processing device includes a blender and a display quality enhancer. The blender is configured to receive a plurality of layer data, generate first image data by blending the plurality of layer data, the first image data including a plurality of pixel values corresponding to a screen in a display device, and generate pixel map data including a plurality of pixel identifications (IDs) based on the plurality of layer data, the plurality of layer data representing a plurality of images to be displayed on the screen, the plurality of pixel IDs indicating display quality enhancement algorithms to be applied to the plurality of pixel values. The display quality enhancer is configured to generate second image data including a plurality of display quality enhancement pixel values by applying the display quality enhancement algorithms to the plurality of pixel values based on the first image data and the pixel map data.

    SYSTEM AND METHODS FOR LOW COMPLEXITY LIST DECODING OF TURBO CODES AND CONVOLUTIONAL CODES

    公开(公告)号:US20190173498A1

    公开(公告)日:2019-06-06

    申请号:US16272722

    申请日:2019-02-11

    Abstract: Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector LAPP; performing Cyclic Redundancy Check (CRC) on LAPP, and stopping if LAPP passes CRC; otherwise, determining magnitudes of LLRs in LAPP; identifying K LLRs in LAPP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting Lmax to maximum magnitude of LLRs in LAPP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}A(r(k))=LA(r(k))−Lmaxvksign[LAPP(r(k))], for k=1, 2, . . . , K; decoding with {tilde over (L)}A to identify {tilde over (L)}APP, wherein {tilde over (L)}APP is LLR vector; and performing CRC on {tilde over (L)}APP, and stopping if {tilde over (L)}APP passes CRC or v=2K-1; otherwise, incrementing v and returning to generating {tilde over (L)}A(r(k)).

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