Abstract:
An neural network (NN) processor includes an input feature map buffer configured to store an input feature matrix, a weight buffer configured to store a weight matrix trained in a form of a, a transform circuit configured to perform a Walsh-Hadamard transform on an input feature vector obtained from the input feature matrix and a weight vector included in the weight matrix to output a transformed input feature vector and a transformed weight vector, and an arithmetic circuit configured to perform an element-wise multiplication (EWM) on the transformed input feature vector and the transformed weight vector.
Abstract:
A method and system are provided. The method includes performing channel estimation on a reference signal (RS), compressing, with a neural network, the channel estimation of the RS, decompressing, with the neural network, the compressed channel estimation, and interpolating the decompressed channel estimation.
Abstract:
A method and an apparatus are provided for determining whether an enhanced physical downlink control channel (ePDCCH) transmission exists for a user equipment (UE) in a subframe. The UE receives a transmission on physical downlink control channel (PDCCH) resources of the subframe. Downlink control information (DCI) is extracted from the PDCCH resources. The DCI includes at least one bit indicating whether the ePDCCH transmission exists for the UE in the subframe. The UE determines whether the ePDCCH transmission exists using the at least one bit. Additional symbols of the subframe are buffered and decoded when the ePDCCH transmission exists.
Abstract:
A system, method and device for object identification is provided. The method of identifying objects includes, but is not limited to, calculating feature vectors of the object, calculating feature vectors of the object's context and surroundings, combining feature vectors of the object, calculating likelihood metrics of combined feature vectors, calculating verification likelihood metrics against contact list entries, calculating a joint verification likelihood metric using the verification likelihood metrics, and identifying the object based on the joint verification likelihood metric.
Abstract:
A method and system for decoding a signal are provided. The method includes receiving a signal, where the signal includes at least one symbol; decoding the signal in stages, where each at least one symbol is decoded into at least one bit per stage, wherein a Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining the magnitudes of the LLRs; identifying K bits of the signal with the smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with the largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords, and stopping after a first candidate codeword passes the CRC.
Abstract:
A method, system, and non-transitory computer-readable recording medium of decoding a signal are provided. The method includes receiving signal to be decoded, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining magnitudes of the LLRs; identifying K bits of the signal with smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords; and stopping after a first candidate codeword passes the CRC.
Abstract:
A method, apparatus, and chipset are provided for constructing hybrid automatic repeat request (HARQ) rate-compatible polar codes for communication channels. The method includes constructing, in a terminal, a base polar code of length 2n; and determining a sequence of m
Abstract:
An image processing device includes a blender and a display quality enhancer. The blender is configured to receive a plurality of layer data, generate first image data by blending the plurality of layer data, the first image data including a plurality of pixel values corresponding to a screen in a display device, and generate pixel map data including a plurality of pixel identifications (IDs) based on the plurality of layer data, the plurality of layer data representing a plurality of images to be displayed on the screen, the plurality of pixel IDs indicating display quality enhancement algorithms to be applied to the plurality of pixel values. The display quality enhancer is configured to generate second image data including a plurality of display quality enhancement pixel values by applying the display quality enhancement algorithms to the plurality of pixel values based on the first image data and the pixel map data.
Abstract:
Apparatuses (including user equipment (UE) and modern chips for UEs), systems, and methods for UE downlink Hybrid Automatic Repeat reQuest (HARQ) buffer memory management are described. In one method, the entire UE DL HARQ buffer memory space is pre-partitioned according to the number and capacities of the UE's active carrier components. In another method, the UE DL HARQ buffer is split between on-chip and off-chip memory so that each partition and sub-partition is allocated between the on-chip and off-chip memories in accordance with an optimum ratio.
Abstract:
Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector LAPP; performing Cyclic Redundancy Check (CRC) on LAPP, and stopping if LAPP passes CRC; otherwise, determining magnitudes of LLRs in LAPP; identifying K LLRs in LAPP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting Lmax to maximum magnitude of LLRs in LAPP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}A(r(k))=LA(r(k))−Lmaxvksign[LAPP(r(k))], for k=1, 2, . . . , K; decoding with {tilde over (L)}A to identify {tilde over (L)}APP, wherein {tilde over (L)}APP is LLR vector; and performing CRC on {tilde over (L)}APP, and stopping if {tilde over (L)}APP passes CRC or v=2K-1; otherwise, incrementing v and returning to generating {tilde over (L)}A(r(k)).