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1.
公开(公告)号:US11171211B1
公开(公告)日:2021-11-09
申请号:US16900788
申请日:2020-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hong-Hyun Park , Zhengping Jiang , Hesameddin Ilatikhameneh , Woosung Choi , Chihak Ahn
Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.
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2.
公开(公告)号:US20210351270A1
公开(公告)日:2021-11-11
申请号:US16900788
申请日:2020-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hong-Hyun Park , Zhengping Jiang , Hesameddin Ilatikhameneh , Woosung Choi , Chihak Ahn
Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.
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