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    ELECTRONIC DEVICE AND NOISE CANCELING METHOD THEREOF
    1.
    发明申请
    ELECTRONIC DEVICE AND NOISE CANCELING METHOD THEREOF 有权

    公开(公告)号：US20170127202A1

    公开(公告)日：2017-05-04

    申请号：US15287959

    申请日：2016-10-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hojun KIM ,  Jinhee WON ,  Daechul JEONG ,  Sungbin HONG

    IPC: H04R29/00 ,  H05K5/02 ,  H05K5/00

    CPC classification number: H04R29/001 ,  H04B1/18 ,  H04R2420/05 ,  H04R2499/11 ,  H05K5/0017 ,  H05K5/0086 ,  H05K5/0247

    Abstract: An electronic device and noise canceling method thereof is provided. The electronic device may include a housing; at least one output circuit arranged inside the housing and configured to generate a first signal; an opening formed on one side of the housing; a hole connected to the opening; a receptacle arranged inside the hole, and configured to receive an external connector, and electrically connected to the at least one output circuit; at least one sensor arranged within a predetermined proximity range to at least one of the opening and the receptacle; and a control circuit electrically connected electrically to the at least one output circuit, the receptacle, and the at least one sensor, wherein the control circuit is configured to detect the external connector approaching to at least one of the opening and the receptacle using the at least one sensor, to generate a second signal upon detection of the approaching external connector, and to control the at least one output circuit to change the first signal at least partly based on the second signal.

    INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS
    2.
    发明公开
    INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS 审中-公开

    公开(公告)号：US20240088015A1

    公开(公告)日：2024-03-14

    申请号：US18462049

    申请日：2023-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeewoong KIM ,  Hojun KIM ,  Sungmoon LEE ,  Seungmin CHA

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/58

    CPC classification number: H01L23/5223 ,  H01L23/5286 ,  H01L23/585

    Abstract: An integrated circuit device comprising: a dielectric layer; a first power delivery network layer on a first surface of the dielectric layer; a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface in a vertical direction; and a via capacitor between the first surface and the second surface of the dielectric layer, wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction, and a first end portion and a second end portion that is opposite to the first end portion of the via capacitor are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230352562A1

    公开(公告)日：2023-11-02

    申请号：US18296511

    申请日：2023-04-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hojun KIM

    IPC: H01L29/66 ,  H01L23/528 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L29/66545 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes a semiconductor layer including first conductivity-type impurities; first active structures extending upwardly from the semiconductor layer and including the first conductivity-type impurities; an epitaxial layer in the semiconductor layer and including second conductivity-type impurities; second active structures extending upwardly from the epitaxial layer, between the first active structures in a first direction, and including the second conductivity-type impurities; third active structures extending upwardly from the epitaxial layer, between the second active structures in the first direction, and including the first conductivity-type impurities; and dummy gate structures intersecting the first and second active structures on the semiconductor layer, respectively, and extending in a second direction.

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