公开(公告)号：US20240237564A1

公开(公告)日：2024-07-11

申请号：US18236651

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwan CHUNG ,  Zhe WU ,  Jung Moo LEE ,  Hideki HORII

IPC: H10N70/00 ,  C22C30/00 ,  H10B63/00 ,  H10B63/10 ,  H10N70/20

CPC classification number: H10N70/8828 ,  C22C30/00 ,  H10B63/10 ,  H10B63/24 ,  H10N70/231

Abstract: A variable resistance memory device includes a first electrode; a variable resistance material on the first electrode; and a second electrode on the variable resistance material, wherein the variable resistance material includes an impurity (A) and is represented as ApGexSbyTez, an atomic concentration ‘x’ of the germanium is 0.4≤x≤0.5, an atomic concentration ‘z’ of the tellurium is 0.3≤z

公开(公告)号：US20210167285A1

公开(公告)日：2021-06-03

申请号：US16898686

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hideki HORII ,  Jungmoo LEE

IPC: H01L45/00

Abstract: A variable resistance memory device includes a first electrode on a substrate, a variable resistance pattern on the first electrode, a second electrode on the variable resistance pattern, a selection pattern structure on the second electrode, and a third electrode on the selection pattern structure. The selection pattern structure may include a first leakage current prevention pattern and a selection pattern sequentially stacked, and the first leakage current pattern may include a two-dimensional transition metal dichalcogenide (TMDC) material.

公开(公告)号：US20180040818A1

公开(公告)日：2018-02-08

申请号：US15401474

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Kyu YANG ,  Seong Geon PARK ,  Dong Jun SEONG ,  Dong Ho AHN ,  Jung Moo LEE ,  Seol CHOI ,  Hideki HORII

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1641 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/76 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

公开(公告)号：US20170250222A1

公开(公告)日：2017-08-31

申请号：US15294873

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Zhe WU ,  Soon-Oh PARK ,  Jeong-HEE PARK ,  Dong-Ho AHN ,  Hideki HORII

IPC: H01L27/24 ,  H01L43/08 ,  H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1675 ,  H01L45/1683

Abstract: A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.