公开(公告)号：US09111880B2

公开(公告)日：2015-08-18

申请号：US14499948

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC: G03F7/26 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract translation: 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US08846304B2

公开(公告)日：2014-09-30

申请号：US13845851

申请日：2013-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC: G03F7/26 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract translation: 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US08952423B2

公开(公告)日：2015-02-10

申请号：US13785156

申请日：2013-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joong-Won Jeon ,  Hee-Sung Kang ,  Dae-Ho Yoon ,  Dal-Hee Lee ,  Suk-Joo Lee

IPC: H01L27/02 ,  H01L29/94

CPC classification number: H01L27/0207 ,  H01L29/94

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract translation: 半导体器件包括布置在半导体器件的中心区域中的逻辑区域和设置在其外部区域中的周边区域。 逻辑区域包括线形逻辑晶体管和盒形去耦电容器。 周边区域包括线形外围晶体管和与外围晶体管相邻设置的线状外围虚拟晶体管。

公开(公告)号：US20150017804A1

公开(公告)日：2015-01-15

申请号：US14499948

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC: H01L21/3213 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract translation: 描述了在半导体器件中形成图案的方法。 提供分为单元和外围区域的基板，在基板上形成对象层。 沿着第一方向在单元区域中的对象层上形成缓冲图案。 沿着单元区域中的缓冲图案的侧壁形成间隔物，并且在外围区域中的目标层上残留有硬掩模层。 去除缓冲层，并且沿着与第一方向不同的第二方向分离间隔物，从而形成单元硬掩模图案。 在外围区域形成外围硬掩模图案。 使用基板中的单元和外围硬掩模图案形成微小图案。 因此，由于光刻工艺引起的线宽变化或边缘线粗糙度被最小化。

公开(公告)号：US20130230979A1

公开(公告)日：2013-09-05

申请号：US13845851

申请日：2013-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC: H01L21/311

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

公开(公告)号：US20160005624A1

公开(公告)日：2016-01-07

申请号：US14818198

申请日：2015-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ryul Ryou ,  Hee-Sung Kang

IPC: H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/32139 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76895

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.