公开(公告)号：US20190386099A1

公开(公告)日：2019-12-19

申请号：US16214659

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20240063259A1

公开(公告)日：2024-02-22

申请号：US18499436

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0649 ,  H01L29/6656 ,  H01L29/42376 ,  H01L27/0924 ,  H01L29/7851 ,  H01L29/6681 ,  H01L29/4916 ,  H01L21/76224

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20220077284A1

公开(公告)日：2022-03-10

申请号：US17526840

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20200098681A1

公开(公告)日：2020-03-26

申请号：US16381243

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Hun Kim ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/417

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.