公开(公告)号：US20180040571A1

公开(公告)日：2018-02-08

申请号：US15628349

申请日：2017-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEON-WOO JANG ,  JUNGHWAN PARK ,  RAMAKANTH KAPPAGANTHU ,  SUNGJIN KIM ,  JUNYONG NOH ,  JUNG-HOON HAN ,  SEUNG SOO KIM ,  SUNGJIN KIM ,  SOJUNG LEE

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/3512

Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.

公开(公告)号：US20230146012A1

公开(公告)日：2023-05-11

申请号：US17954394

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEON-WOO JANG ,  DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  SOOHO SHIN ,  JIHOON CHANG

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10897

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.

公开(公告)号：US20230041059A1

公开(公告)日：2023-02-09

申请号：US17857395

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  Joonsuk PARK ,  JIHOON CHANG ,  HYEON-WOO JANG

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

公开(公告)号：US20160035714A1

公开(公告)日：2016-02-04

申请号：US14875385

申请日：2015-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUN-NAM KIM ,  SUN-YOUNG PARK ,  SOO-HO SHIN ,  KYE-HEE YEOM ,  HYEON-WOO JANG ,  JIN-WON JEONG ,  CHANG-HYUN CHO ,  HYEONG-SUN HONG

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。