公开(公告)号：US20230328951A1

公开(公告)日：2023-10-12

申请号：US18097675

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SIK PARK ,  SOOHO SHIN ,  CHEOLHO BAEK

IPC: H10B12/00

CPC classification number: H10B12/033 ,  H10B12/50 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a cell array region, a data storage structure provided on the cell array region of the substrate, the data storage structure including a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, a blocking layer provided on a top surface of the top electrode, a lower interlayer insulating layer provided on the blocking layer, and a lower contact penetrating the lower interlayer insulating layer and electrically connected to the top electrode. At least a portion of a side surface of the lower contact may contact the blocking layer.

公开(公告)号：US20230146012A1

公开(公告)日：2023-05-11

申请号：US17954394

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEON-WOO JANG ,  DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  SOOHO SHIN ,  JIHOON CHANG

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10897

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.