公开(公告)号：US11095271B2

公开(公告)日：2021-08-17

申请号：US16224850

申请日：2018-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun-Il Kang ,  June-Hee Lee ,  Byung-Wook Cho

IPC: H03H17/06 ,  H03H17/02 ,  H04L27/01

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

公开(公告)号：US11515859B2

公开(公告)日：2022-11-29

申请号：US17372744

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun-Il Kang ,  June-Hee Lee ,  Byung-Wook Cho

IPC: H03H17/06 ,  H03H17/02 ,  H04L27/01

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

公开(公告)号：US10728061B2

公开(公告)日：2020-07-28

申请号：US16253589

申请日：2019-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： June-Hee Lee ,  Byungwook Cho ,  Bongkyu Kim ,  Gun-Il Kang

IPC: H04L25/03

Abstract: An electronic device includes a reception equalizer that performs, a first equalization on a first signal based on a first coefficient, and one or more second equalizations on one or more second signals based on the first coefficient, the one or more second signals being based on a second coefficient associated with one or more characteristics of a transmission equalizer of the external device, and circuitry that iteratively sends control information generated based on the first coefficient to the external device until a termination condition is satisfied with regard to the first coefficient, the control information causing the second coefficient to be increased or decreased, the iteratively sent control information causing a first absolute value of the first coefficient corresponding to a final equalization of the one or more second equalizations to become smaller than a second absolute value of the first coefficient corresponding to the first equalization.

公开(公告)号：US09720438B2

公开(公告)日：2017-08-01

申请号：US14635145

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hee Lee ,  Bong-Kyu Kim ,  Dong-Chul Choi ,  Gun-Il Kang

IPC: G06F1/12 ,  G06F13/42 ,  G06F1/10 ,  G06F13/40 ,  G06F1/14

CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  G06F13/4022

Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.