公开(公告)号：US20240088118A1

公开(公告)日：2024-03-14

申请号：US18508663

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/16 ,  H01L27/016 ,  H01L28/90 ,  H01L2224/08147 ,  H01L2224/16147

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20210118848A1

公开(公告)日：2021-04-22

申请号：US16883153

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee JANG ,  Kyung Suk OH ,  Eunseok SONG ,  Seung-Yong CHA

IPC: H01L25/065 ,  H01L25/18

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

公开(公告)号：US20230101041A1

公开(公告)日：2023-03-30

申请号：US17743819

申请日：2022-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok SONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A three-dimensional (3D) laminated chip that includes a first semiconductor chip including a first through electrode disposed therein. A second semiconductor chip is arranged horizontally adjacent to the first semiconductor chip. A third semiconductor chip is arranged on the first semiconductor chip and the second semiconductor chip. A size of the third semiconductor chip is greater than a size of the first semiconductor chip.

公开(公告)号：US20220165721A1

公开(公告)日：2022-05-26

申请号：US17369228

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L27/01 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20240213143A1

公开(公告)日：2024-06-27

申请号：US18541147

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok SONG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/08155 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate, an interposer above the package substrate, a connection terminal between the package substrate and the interposer, a first semiconductor chip and a second semiconductor chip above the interposer, a bridge in the interposer, the bridge connected to the first semiconductor chip and the second semiconductor chip, a capacitor structure in the interposer, the capacitor structure including an upper structure including an upper capacitor and a lower structure including a lower capacitor, and a chip connection terminal including at least one first chip connection terminal between the interposer and the first semiconductor chip and at least one second chip connection terminal between the interposer and the second semiconductor chip.

公开(公告)号：US20220415775A1

公开(公告)日：2022-12-29

申请号：US17687796

申请日：2022-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok SONG ,  Kyung Suk OH

IPC: H01L23/498 ,  H01L25/065

Abstract: A semiconductor package is disclosed. The semiconductor package may include a package substrate, an upper semiconductor chip on the package substrate, and a lower semiconductor chip between the package substrate and the upper semiconductor chip. The upper semiconductor chip may include a core region having a power circuit thereon and a logic cell region having a logic circuit thereon. The lower semiconductor chip may include a power wire region vertically overlapping the core region. The lower semiconductor chip may include a first substrate, a first through electrode, and a second through electrode, the first substrate including an active surface having an integrated circuit thereon, and a first through electrode and a second through electrode penetrating the first substrate in the power wire region. A distance between the first and second through electrodes may be smaller than a width of the first through electrode.

公开(公告)号：US20220328454A1

公开(公告)日：2022-10-13

申请号：US17853140

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee JANG ,  Kyung Suk OH ,  Eunseok SONG ,  Seung-Yong CHA

IPC: H01L25/065 ,  H01L25/18

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.