公开(公告)号：US20240251545A1

公开(公告)日：2024-07-25

申请号：US18493924

申请日：2023-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Seong PARK ,  Seung Hee LEE ,  Yong-Suk TAK ,  Dong-Gyu KIM ,  Yu Rim KIM ,  Tae Won KIM ,  Dong-Hyeon LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: There is provided a semiconductor memory device having improved integration and electrical characteristics. The semiconductor memory device includes a bit line extending in a first direction on a substrate, a first channel pattern disposed on the bit line, a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction, a first word line disposed between the first channel pattern and the second channel pattern extends in a second direction, a second word line disposed between the first channel pattern and the second channel pattern, extends in the second direction, and is spaced apart from the first word line in the first direction, and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga) and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.

公开(公告)号：US20250107065A1

公开(公告)日：2025-03-27

申请号：US18619490

申请日：2024-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Seong PARK ,  Jihyun KHO ,  Seunghee LEE ,  Yurim KIM ,  Yong-Suk TAK ,  Dong-Gyu KIM

IPC: H10B12/00

Abstract: A semiconductor device includes a semiconductor pattern, a dielectric layer on the semiconductor pattern, and a conductive pattern on the dielectric layer. Each of the semiconductor pattern and the dielectric layer includes impurities. The dielectric layer includes a concentration profile of impurities including a first variation section including a first concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, and a second variation section including a second concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern.