公开(公告)号：US12266419B2

公开(公告)日：2025-04-01

申请号：US17944414

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dojeon Lee ,  Junehong Park ,  Kichang Jang

IPC: G11C7/04 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10

Abstract: A semiconductor device includes a first voltage generating circuit configured to output a first voltage based on temperature; an analog-to-digital converter configured to convert the first voltage into a temperature code; a code conversion logic configured to output an offset code and a level code of a temperature section which the temperature belongs among temperature sections based on the temperature code; an offset voltage generating circuit configured to output an offset voltage based on the offset code; a second voltage generating circuit configured to output a second voltage having a constant value within a temperature section based on the level code; and a temperature compensation voltage generating circuit configured to receive the first voltage, the second voltage, the offset voltage, and a feedback voltage and output a temperature compensation voltage, the feedback voltage based on the first voltage, the second voltage, and the offset voltage.

公开(公告)号：US11244721B2

公开(公告)日：2022-02-08

申请号：US16821265

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dojeon Lee ,  Dueung Kim ,  Jin-Young Kim

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.