公开(公告)号：US10332587B1

公开(公告)日：2019-06-25

申请号：US15986354

申请日：2018-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Jong Sung ,  Dae Sun Kim ,  Jin Seon Kim ,  In Cheol Nam

IPC: G11C11/24 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs. When the first sub word line may be selected, a predetermined voltage may be applied to the plurality of dummy bit lines for a first predetermined period in which a charge sharing operation is performed on the plurality of first memory cells connected to the selected one of the plurality of first sub word lines.

公开(公告)号：US20190180812A1

公开(公告)日：2019-06-13

申请号：US15986354

申请日：2018-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Jong Sung ,  Dae Sun Kim ,  Jin Seon Kim ,  In Cheol Nam

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4099 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a first sub memory cell array block including a plurality of first memory cells between a plurality of first sub word lines, and a plurality of first odd-numbered bit lines and a plurality of dummy bit lines and includes a second sub memory cell array block including a plurality of second memory cells between a plurality of second sub word lines, a plurality of second odd-numbered bit lines, and a plurality of second even-numbered bit lines. The memory cell array may be arranged to have an open bit line architecture in which the plurality of first odd-numbered bit lines and the plurality of second even-numbered bit lines form bit line pairs. When the first sub word line may be selected, a predetermined voltage may be applied to the plurality of dummy bit lines for a first predetermined period in which a charge sharing operation is performed on the plurality of first memory cells connected to the selected one of the plurality of first sub word lines.

公开(公告)号：US10811079B2

公开(公告)日：2020-10-20

申请号：US16268807

申请日：2019-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Min Park ,  Dae Sun Kim ,  In Cheol Nam ,  Chang Soo Lee ,  Jin Seok Jeong

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/408

Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.

公开(公告)号：US20200111520A1

公开(公告)日：2020-04-09

申请号：US16268807

申请日：2019-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Min Park ,  Dae Sun Kim ,  In Cheol Nam ,  Chang Soo Lee ,  Jin Seok Jeong

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.

公开(公告)号：US10319726B2

公开(公告)日：2019-06-11

申请号：US15642394

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Cheol Nam ,  Sung Hee Han ,  Dae Sun Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/765 ,  H01L27/108

Abstract: A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.