公开(公告)号：US20220416045A1

公开(公告)日：2022-12-29

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20240162228A1

公开(公告)日：2024-05-16

申请号：US18219875

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu LEE ,  Hyungjoo NA ,  Jinchan YUN ,  Cheoljin YUN ,  Kyuman HWANG

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional semiconductor device includes a lower connection structure; a device structure; and an upper connection structure sequentially disposed along a first direction, wherein the device structure includes a substrate on the lower connection structure; first and second source/drain patterns on the substrate; a separation pattern adjacent in a second direction to the source/drain patterns, the second direction being parallel to a bottom surface of the substrate; and a through conductive pattern adjacent in a third direction to the separation pattern, the third direction being parallel to the bottom surface of the substrate and intersecting the second direction, the through conductive pattern connects the lower connection structure and the upper connection structure to each other, and the through conductive pattern is connected either through the lower connection structure to the first source/drain pattern or through the upper connection structure to the second source/drain pattern.

公开(公告)号：US20240204068A1

公开(公告)日：2024-06-20

申请号：US18224864

申请日：2023-07-21

Applicant: Samsung electronics Co., Ltd.

Inventor： HYUNGJOO NA ,  WOO BIN SONG ,  JIN-WOOK YANG ,  Cheoljin YUN ,  YOSHINAO HARADA

IPC: H01L29/417 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked, a source/drain pattern connected to the plurality of semiconductor patterns, a through pattern penetrating the source/drain pattern, a metal-semiconductor compound layer between the source/drain pattern and the through pattern, a gate electrode on the plurality of semiconductor patterns, the gate electrode including inner electrodes between adjacent semiconductor patterns of the plurality of semiconductor patterns and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns, an active contact on the through pattern, and a first metal layer on the active contact, the first metal layer including a power wiring and first wirings connected to the active contact.

公开(公告)号：US20240120401A1

公开(公告)日：2024-04-11

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.