TRANSISTOR ARRAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20210225977A1

    公开(公告)日:2021-07-22

    申请号:US17225174

    申请日:2021-04-08

    Inventor: Hyuk Soon KWON

    Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

    TRANSISTOR ARRAY PANEL, INCLUDING A SOURCE CONNECTING MEMBER AND A DRAIN CONNECTING MEMBER MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20200083308A1

    公开(公告)日:2020-03-12

    申请号:US16686033

    申请日:2019-11-15

    Inventor: Hyuk Soon KWON

    Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

    TRANSISTOR ARRAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20230371309A1

    公开(公告)日:2023-11-16

    申请号:US18226251

    申请日:2023-07-26

    Inventor: Hyuk Soon KWON

    CPC classification number: H10K59/1213 H10K59/131 H01L27/1214 H10K71/00

    Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

    TRANSISTOR ARRAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20170294498A1

    公开(公告)日:2017-10-12

    申请号:US15481273

    申请日:2017-04-06

    Inventor: Hyuk Soon KWON

    Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.

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