公开(公告)号：US20160224165A1

公开(公告)日：2016-08-04

申请号：US14833358

申请日：2015-08-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： So Young KOO ,  Jong Chan LEE ,  Yoon Ho KHANG ,  Sun Haeng CHO

IPC: G06F3/041

CPC classification number: G06F3/044 ,  G06F3/041 ,  G06F3/0412 ,  G06F2203/04103

Abstract: A touch screen panel includes a substrate, a plurality of touch electrodes in a touch area of the substrate, the touch electrodes sensing a touch, a connection line connected to a touch electrode of the plurality of touch electrodes, and a pad connected to one end of the connection line. The pad includes a first pad, a second pad on the first pad within a boundary line of the first pad, and a third pad covering a top surface and a side surface of the second pad.

Abstract translation: 触摸屏面板包括基板，在基板的触摸区域中的多个触摸电极，感测触摸的触摸电极，连接到多个触摸电极的触摸电极的连接线以及连接到一端的焊盘 的连接线。 焊盘包括第一焊盘，位于第一焊盘的边界线内的第一焊盘上的第二焊盘，以及覆盖第二焊盘的顶表面和侧表面的第三焊盘。

公开(公告)号：US20160148958A1

公开(公告)日：2016-05-26

申请号：US15010497

申请日：2016-01-29

Applicant: Samsung Display Co., Ltd.

Inventor： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract translation: 薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。

公开(公告)号：US20140138772A1

公开(公告)日：2014-05-22

申请号：US13892574

申请日：2013-05-13

Applicant: Samsung Display Co., Ltd

Inventor： Hyun Jae NA ,  Yoon Ho KHANG ,  Sang Ho PARK ,  Dong Hwan SHIM ,  Se Hwan YU ,  Yong Su LEE ,  Myoung Geun CHA

IPC: H01L27/12

CPC classification number: H01L29/4908 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78633

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管显示面板包括基板，形成在基板上的第一绝缘层，形成在第一绝缘层上的半导体层，形成在半导体层上的第二绝缘层，以及 形成在第二绝缘层上的栅电极，其中第一绝缘层包括遮光材料，第一绝缘层的厚度大于或等于第二绝缘层的厚度。

公开(公告)号：US20240413248A1

公开(公告)日：2024-12-12

申请号：US18808905

申请日：2024-08-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H10K59/121

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20180240910A1

公开(公告)日：2018-08-23

申请号：US15901137

申请日：2018-02-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yoon Ho KHANG ,  Doo Na KIM ,  Myoung Geun CHA

IPC: H01L29/786 ,  H01L21/3115 ,  H01L29/66

CPC classification number: H01L29/78603 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31155 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/3262 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78666 ,  H01L29/78675

Abstract: A transistor includes a buffer layer, an active pattern, and a first insulating layer. The buffer layer is doped with an impurity. The active pattern is on the buffer layer and includes a channel area between a source area and a drain area. The first insulating layer is on the active pattern. A gate electrode is on the first insulating layer and overlaps the channel area. A source electrode is insulated from the gate electrode and is electrically coupled with the source area. A drain electrode is insulated from the gate electrode and is electrically coupled with the drain area.

公开(公告)号：US20150021602A1

公开(公告)日：2015-01-22

申请号：US14508766

申请日：2014-10-07

Applicant: Samsung Display Co., Ltd.

Inventor： Su-Hyoung KANG ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA

IPC: H01L27/12 ,  H01L23/31 ,  H01L23/29 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/1248 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. Source and drain electrodes of the thin film transistor each include a lower layer and an upper layer. A first passivation layer contacts the lower layer of the source and drain electrodes but does not contact the upper layer of the source and drain electrodes, and a second passivation layer is disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.

Abstract translation: 一种薄膜晶体管阵列面板和能够形成由不同材料制成的绝缘层的制造方法，用于与氧化物半导体和第二部分接触的部分，而不需要额外的工艺。 薄膜晶体管的源极和漏极各自包括下层和上层。 第一钝化层接触源电极和漏电极的下层，但不接触源极和漏极的上层，并且第二钝化层设置在源极和漏极的上层。 第一钝化层可以由氧化硅制成，并且第二钝化可以由氮化硅制成。

公开(公告)号：US20230215954A1

公开(公告)日：2023-07-06

申请号：US18176454

申请日：2023-02-28

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： YONG SU LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung Kim ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L29/78618 ,  H01L27/1288 ,  H01L27/124 ,  H01L29/7869 ,  H01L27/1225 ,  H01L29/78696 ,  H01L29/66969 ,  H01L29/41733 ,  H10K59/1213

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20170154897A1

公开(公告)日：2017-06-01

申请号：US15427696

申请日：2017-02-08

Applicant: Samsung Display Co., Ltd.

Inventor： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

公开(公告)号：US20150194534A1

公开(公告)日：2015-07-09

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。