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公开(公告)号：US20160173098A1
公开(公告)日：2016-06-16
申请号：US14877869
申请日：2015-10-07
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
IPC: H03K19/0185
CPC classification number: H03K19/018528
Abstract: A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.
Abstract translation: 电流模式逻辑缓冲器包括一个包括第一输入晶体管和第二输入晶体管的输入晶体管的差分对，与第一输入晶体管串联耦合的第一输出负载电阻器，与第二输入晶体管串联耦合的第二输出负载电阻器 在所述第一输出负载电阻器和所述第一输入晶体管之间的第一节点处的第一输出，在所述第二输出负载电阻器和所述第二输入晶体管之间的第二节点处的第二输出;第一保持电容器，被配置为提供半常数 经由第一低电阻路径将电压源提供给第一输出;以及第二保持电容器，被配置为经由第二低电阻路径向第二输出提供半恒定电压源。
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公开(公告)号：US09906195B2
公开(公告)日：2018-02-27
申请号：US14946704
申请日：2015-11-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
CPC classification number: H03F1/42 , G09G3/2085 , G09G2300/0833 , G09G2310/0291 , H03F3/193 , H03F2200/174
Abstract: An amplifier including: an input terminal coupled to a first node; an output terminal coupled to a second node; and a transistor coupled between a first power source and a second power source, the transistor including: a gate electrode coupled to the first node; a drain electrode coupled to the second node; a source electrode coupled to a third node; and a bulk electrode coupled to a fourth node and configured to receive a bulk voltage to change a threshold voltage of the transistor.
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公开(公告)号：US09197395B2
公开(公告)日：2015-11-24
申请号：US14465739
申请日：2014-08-21
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Amir Amirkhany , Nasrin Jaffari
CPC classification number: H04L7/0012 , G09G5/008 , G09G2320/0693 , G09G2370/08 , H04L7/0338 , H04L43/087 , H04N5/04
Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
Abstract translation: 用于将采样率时钟与数据一起转发的系统。 在一个实施例中，采样率时钟由发射机连同数据发送到一个或多个接收机。 接收机使用接收到的采样时钟对接收到的数据进行采样。 发射机中的延迟调整电路使用在接收机和发射机之间的后向通道中实现的延迟误差感测和校正来调整每个发送的数据流的延迟。
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公开(公告)号：US20150160679A1
公开(公告)日：2015-06-11
申请号：US14548187
申请日：2014-11-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
IPC: G05F3/26
Abstract: A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.
Abstract translation: 电路包括：共源共栅电流源，包括：电流镜晶体管; 和共源共栅晶体管; 以及耦合到所述共源共栅电流源的偏置电路，所述偏置电路包括：电流源; 与电流源串联耦合的第一晶体管，以形成穿过电流源和第一晶体管的第一电流路径; 与电流源串联耦合的第二晶体管; 以及与所述第二晶体管和所述电流源串联耦合的第三晶体管，以形成通过所述电流源和所述第二和第三晶体管的第二电流路径，其中所述第三晶体管的沟道尺寸大于所述第二晶体管的沟道尺寸， 根据偏置电路的设计因子确定的倍数。
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公开(公告)号：US09614530B2
公开(公告)日：2017-04-04
申请号：US14877869
申请日：2015-10-07
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
IPC: H03K19/0185
CPC classification number: H03K19/018528
Abstract: A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.
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Patent Agency Ranking
公开(公告)号：US20150015326A1
公开(公告)日：2015-01-15
申请号：US14258926
申请日：2014-04-22
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
IPC: H03K17/687
CPC classification number: H03K17/687 , G05F3/205
Abstract: A bulk-modulated current source includes: an output terminal configured to supply an output current; a first transistor comprising: a first electrode coupled to the output terminal, a second electrode, a bulk electrode, and a gate electrode configured to receive a bias voltage; and an amplifier comprising: an input terminal electrically coupled to the first electrode of the first transistor, and an output terminal electrically coupled to the bulk electrode of the first transistor.
Abstract translation: 体积调制电流源包括：输出端子，被配置为提供输出电流; 第一晶体管，包括：耦合到所述输出端子的第一电极，第二电极，体电极和被配置为接收偏置电压的栅电极; 以及放大器，包括：电耦合到所述第一晶体管的所述第一电极的输入端子，以及电耦合到所述第一晶体管的体电极的输出端子。
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公开(公告)号：US08817184B1
公开(公告)日：2014-08-26
申请号：US14180243
申请日：2014-02-13
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Nasrin Jaffari
CPC classification number: H04L7/0012 , G09G5/008 , G09G2320/0693 , G09G2370/08 , H04L7/0338 , H04L43/087 , H04N5/04
Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
Abstract translation: 用于将采样率时钟与数据一起转发的系统。 在一个实施例中，采样率时钟由发射机连同数据发送到一个或多个接收机。 接收机使用接收到的采样时钟对接收到的数据进行采样。 发射机中的延迟调整电路使用在接收机和发射机之间的后向通道中实现的延迟误差感测和校正来调整每个发射数据流的延迟。
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公开(公告)号：US20150054586A1
公开(公告)日：2015-02-26
申请号：US14180287
申请日：2014-02-13
Applicant: Samsung Display Co., Ltd.
Inventor： Nasrin Jaffari
CPC classification number: H03F1/0205 , G05F3/24 , G05F3/262 , H03F1/30 , H03F3/16 , H03F3/45 , H03F2200/18
Abstract: A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.
Abstract translation: 用于偏置场效应晶体管（FET）以提供基本上不受电源电压变化影响的跨导（gm）的偏置电路。 在一个实施例中，电路包括两个并联电流路径，每个包括两个放大元件，例如FET，其中一个路径中的FET都是二极管连接的，而另一个路径中的FET不是二极管连接的。 电源电压的变化导致所有四个FET的电压相当的变化，漏极引起的栅极降低（DIBL）导致gm随电源电压变化的相对小的变化。
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公开(公告)号：US20140294129A1
公开(公告)日：2014-10-02
申请号：US13961767
申请日：2013-08-07
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
IPC: H04B1/10
Abstract: A receiver for receiving digital data after transmission through a channel which produces inter-symbol interference or other distortion. In one embodiment, a received signal is differentiated before being digitized to form an output digital bit stream, to reduce the effects of inter-symbol interference and other distortion in the channel. The differentiated signal is compared to two threshold values, a first threshold value, and a second threshold value, the first threshold value being greater than the second threshold value. When the differentiated signal exceeds the first threshold, the output bit is 1, when the differentiated signal is less than the second threshold value, the output bit is 0, and when the differentiated signal is between the first threshold value and the second threshold value, the output bit is the same as the previous output bit.
Abstract translation: 一种用于在通过产生符号间干扰或其他失真的信道传输之后接收数字数据的接收机。 在一个实施例中，接收信号在数字化之前被微分以形成输出数字比特流，以减少信道中符号间干扰和其他失真的影响。 差分信号与两个阈值（第一阈值）和第二阈值进行比较，第一阈值大于第二阈值。 当微分信号超过第一阈值时，输出比特为1，当微分信号小于第二阈值时，输出比特为0，当微分信号处于第一阈值和第二阈值之间时， 输出位与以前的输出位相同。
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公开(公告)号：US09746869B2
公开(公告)日：2017-08-29
申请号：US14548187
申请日：2014-11-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Nasrin Jaffari
Abstract: A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.
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