公开(公告)号：US20210091923A1

公开(公告)日：2021-03-25

申请号：US16914094

申请日：2020-06-26

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Min Young PARK ,  Jong Min SHIM

IPC: H04L7/033 ,  G09G3/32 ,  H04L7/04 ,  H03L7/08 ,  H03L7/089 ,  H03L7/099 ,  H03L7/095

Abstract: A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

公开(公告)号：US20210065634A1

公开(公告)日：2021-03-04

申请号：US16889683

申请日：2020-06-01

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Jang Hoon KWAK ,  Min Young PARK

IPC: G09G3/3283 ,  H03L7/081 ,  H03L7/08

Abstract: A display device may extract an edge of a data signal based on the data signal and phase conversion clock signals, extract a phase of the data signal based on the edge, and generate a clock phase calibration signal based on the phase of the data signal. The display device may calibrate a phase of a clock signal using the clock phase calibration signal that has a phase corresponding to the phase of the clock signal, thereby improving transmission characteristic of the signal.

公开(公告)号：US20190392766A1

公开(公告)日：2019-12-26

申请号：US16368001

申请日：2019-03-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ki Hyun PYUN ,  Min Young PARK

IPC: G09G3/3266 ,  G09G3/3275 ,  G06F12/02

Abstract: A timing controller includes: a data transmitter which transmits image data and a frame control signal to a data driver; a scan controller which transmits a scan start signal and a scan clock signal through scan control lines; and a memory interface which receives mode data from a control memory through a memory transmission line during a mode period, where the mode period is a period in which the scan controller does not transmit the scan start signal and the scan clock signal to the scan control lines.

公开(公告)号：US20220084453A1

公开(公告)日：2022-03-17

申请号：US17235202

申请日：2021-04-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ki Hyun PYUN ,  Min Young PARK ,  Eun Jin CHOI

IPC: G09G3/20

Abstract: A display device includes: a pixel unit including pixels connected to data lines and scan lines, and signal output lines, where at least one signal output line of the signal output lines is connected to each of the scan lines through a contact point; a data driver disposed at one side of the pixel unit to drive the data lines; a scan driver disposed at the one side of the pixel unit together with the data driver to drive the scan lines; and a timing controller controlling the data driver and the scan driver. The data driver includes: output buffers outputting data signals to the data lines, respectively; and a slew rate controller adjusting a slew rate of the data signals by controlling a bias value supplied to the output buffers in units of pixel rows based on positions of the pixels and a change in the data signals.

公开(公告)号：US20230126165A1

公开(公告)日：2023-04-27

申请号：US18088435

申请日：2022-12-23

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Min Young PARK ,  Jong Min SHIM

IPC: H04L7/033 ,  G09G3/32 ,  H03L7/08 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H04L7/04

Abstract: A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

公开(公告)号：US20160078957A1

公开(公告)日：2016-03-17

申请号：US14660648

申请日：2015-03-17

Applicant: Samsung Display Co., Ltd.

Inventor： Yun Mi KIM ,  Ki Hyun PYUN ,  Sung Jun KIM ,  Min Young PARK ,  Jeong Doo LEE ,  Kyung Hwa LIM

IPC: G11C16/28 ,  G09G5/395 ,  H03M1/66 ,  G11C16/10 ,  G11C16/26

CPC classification number: G09G5/395 ,  G09G3/3648 ,  G09G5/12 ,  G09G5/393 ,  G09G2330/021 ,  G09G2360/12 ,  G11C7/16 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H03M1/66

Abstract: A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Abstract translation: 提供了一种存储器，其包括电可擦除和可编程只读存储器（EEPROM），其被配置为存储操作系统并且响应于写入操作信号可重写，地址比较器被配置为连接到内部集成电路（I2C） 线路，并响应于外部信号将写入操作信号输出到EEPROM;数模转换器（DAC）单元，被配置为响应于外部信号确定是否连接DAC电阻器和I2C线路 - 配置为连接到I2C线路的电阻单元。

公开(公告)号：US20150091883A1

公开(公告)日：2015-04-02

申请号：US14161521

申请日：2014-01-22

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Yun Mi KIM ,  Min Young PARK ,  Sung-Jun KIM ,  Ju Hyun KIM ,  Yong Jae LEE ,  Kyung-Hwa LIM

IPC: G09G3/34

CPC classification number: G09G3/2074 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2320/0252

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract translation: 公开了一种减少将具有多个栅极线的显示装置的栅极线驱动信号从小于全栅极导通电平的电平切换到栅极导通电平的方法。 该方法可以包括：在相应栅极线的栅极线预充电周期期间，使栅极线驱动信号处于完全栅极导通电平; 在预充电周期之后的相应的栅极线主充电期间，使栅极线驱动信号处于全栅极导通电平; 并且在插入在栅极线预充电周期与其对应的栅极线主充电周期之间的插入时段期间，使栅极线驱动信号处于处于完全栅极导通电平之间的中间电平， 关门水平