-
公开(公告)号:US12190824B2
公开(公告)日:2025-01-07
申请号:US18205901
申请日:2023-06-05
Inventor: Kyungho Kim , Keechan Park , Yikyoung You , Sangyong No , Gichang Lee , Nokyung Park , Sunkwun Son , Donghee Shin
IPC: G09G3/3266
Abstract: A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.
-
公开(公告)号:US20250006136A1
公开(公告)日:2025-01-02
申请号:US18626327
申请日:2024-04-04
Applicant: Samsung Display Co., Ltd.
Inventor: Sangyong No , Kyungho Kim
IPC: G09G3/3266
Abstract: A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.
-
公开(公告)号:US11996026B1
公开(公告)日:2024-05-28
申请号:US18215736
申请日:2023-06-28
Applicant: Samsung Display Co., LTD.
Inventor: Kyungho Kim , Gichang Lee
IPC: G09G3/20 , G09G3/3266 , G09G3/36
CPC classification number: G09G3/20 , G09G3/3266 , G09G3/3677 , G09G2300/0819 , G09G2300/0842 , G09G2310/0286 , G09G2310/04 , G09G2330/021 , G09G2340/0435
Abstract: A scan driver includes a plurality of stages. Each of the plurality of stages includes a control circuit which controls a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal and a second clock signal, a carry output circuit which outputs a carry signal in response to the voltage of the first node and the voltage of the second node, an enable node controlling circuit which controls a voltage of an enable node in response to the carry signal, an enable signal and an inverted enable signal, a masking circuit which controls a voltage of a third node in response to the voltage of the second node and the voltage of the enable node, and a scan output circuit which outputs a scan signal in response to the voltage of the first node and the voltage of the third node.
-
公开(公告)号:US11145697B2
公开(公告)日:2021-10-12
申请号:US15864049
申请日:2018-01-08
Applicant: Samsung Display Co., LTD.
Inventor: Jinkoo Chung , Gunhee Kim , Kyungho Kim , Seong-Min Kim , Eunkyoung Nam , Chaungi Choi
IPC: H01L27/32
Abstract: An organic light emitting display device includes a substrate including an emission region and a non-emission region, an organic light emitting element which emits light, the organic light emitting element including a first electrode disposed on the substrate in the emission region, an organic light emitting layer disposed on the first electrode in the emission region, and a second electrode disposed on the organic light emitting layer, and a via insulation layer disposed on the substrate in the non-emission region thereof, the via insulation layer including an organic insulation material. The via insulation layer defines an opening therein in which the organic light emitting layer of the organic light emitting element is disposed.
-
公开(公告)号:US10073304B2
公开(公告)日:2018-09-11
申请号:US15627528
申请日:2017-06-20
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Kyungho Kim , Nahyeon Cha
IPC: G02F1/1339 , G02F1/1335 , G02F1/1362 , G02F1/1337
CPC classification number: G02F1/1339 , G02F1/133512 , G02F1/133514 , G02F1/13378 , G02F1/13394 , G02F1/136286 , G02F2001/133742 , G02F2001/13396
Abstract: A display device includes: a lower substrate including a display area and a non-display area; an upper substrate facing the lower substrate; a sealing portion on the non-display area and between the lower substrate and the upper substrate; an optical transmittance layer between the lower substrate and the upper substrate, and surrounded by the sealing portion; a first light blocking portion on the display area of the lower substrate; and a second light blocking portion on the non-display area of the lower substrate. The second light blocking portion includes a base portion, a barrier wall protruding from the base portion and a protruding portion protruding from the barrier wall. A total height of the second light blocking portion at the base portion thereof is less than a total height of the second light blocking portion at the barrier wall and the protruding portion thereof.
-
公开(公告)号:US20240321217A1
公开(公告)日:2024-09-26
申请号:US18614544
申请日:2024-03-22
Applicant: Samsung Display Co., Ltd.
Inventor: Kyungho Kim , Sangyong No
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2310/0289 , G09G2310/08
Abstract: A driving circuit includes stages, each of the stages including: a first control circuit connected to a first voltage input terminal and a second voltage input terminal, and to control voltage levels of a first control node, a second control node, and a third control node; a first output circuit connected to a first clock terminal and a third voltage input terminal, and to output a first output signal according to the voltage levels of the first control node and the second control node; a second output circuit connected to a second clock terminal and the second voltage input terminal, and to output a second output signal according to the voltage levels of the third control node and the second control node; and a boosting circuit connected to a third clock terminal and the second voltage input terminal, and to boost the voltage level of the first control node.
-
公开(公告)号:US20240321215A1
公开(公告)日:2024-09-26
申请号:US18436904
申请日:2024-02-08
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Kyungho Kim , Sangyong No , Gichang Lee
IPC: G09G3/3266 , G09G3/3233 , H03K17/687
CPC classification number: G09G3/3266 , G09G3/3233 , H03K17/6871 , G09G2300/0842 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A stage of a gate driving circuit includes a first control circuit connected to a first voltage input terminal receiving a first voltage and a second voltage input terminal receiving a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node and a second control node; a first output circuit connected to a first clock terminal and a third voltage input terminal receiving a third voltage, the first output circuit being configured to output a gate signal according to the voltage levels of the first control node and the second control node; and a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a carry signal according to the voltage levels of the first control node and the second control node.
-
公开(公告)号:US10216052B2
公开(公告)日:2019-02-26
申请号:US15823301
申请日:2017-11-27
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Donghee Shin , Kyungho Kim
IPC: G02F1/1345 , G09G3/20 , H01L27/12 , H01L25/065 , G02F1/1368 , G02F1/1362
Abstract: A display device includes a substrate including a plurality of pixels disposed in a display area of the substrate. A non-display area of the substrate is disposed adjacent to the display area. The display device further includes a plurality of gate lines and a plurality of data lines arranged in a matrix form in the display area on the substrate, at least one driver integrated circuit (IC) disposed in the non-display area on the substrate, and a plurality of data fan-out wirings disposed on the substrate and connecting the data lines and the at least one driver IC. Lengths of the data fan-out wirings vary, and the data lines overlap the gate lines more as the lengths of the corresponding data fan-out wirings decrease.
-
公开(公告)号:US10324342B2
公开(公告)日:2019-06-18
申请号:US15592281
申请日:2017-05-11
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Kyungho Kim , Seongyoung Lee , Nahyeon Cha
IPC: G02F1/1345 , G02F1/1335 , G02F1/1339 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G09G3/36
Abstract: A display device includes: a display substrate including a display area and a non-display area adjacent to each other; and an opposing substrate opposing the display substrate. The display substrate includes: a pixel in the display area; a gate driver at the non-display area and including a gate and data wiring; an organic layer on the gate and data wiring; a column spacer on the organic layer; a connection portion connected to the gate and data wiring at contact holes respectively exposing the gate and data wiring; and a protective layer on the connection portion. In a top plan view, the protective layer has a same shape as a shape of the connection portion. The opposing substrate includes a black matrix at the display area to define a pixel area of the pixel and at the non-display area to define the display area and the non-display area.
-
10.
公开(公告)号:US20240054959A1
公开(公告)日:2024-02-15
申请号:US18205901
申请日:2023-06-05
Inventor: Kyungho Kim , Keechan Park , Yikyoung You , Sangyong No , Gichang Lee , Nokyung Park , Sunkwun Son , Donghee Shin
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/0842 , G09G2310/0286
Abstract: A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.
-
-
-
-
-
-
-
-
-