公开(公告)号：US20150107977A1

公开(公告)日：2015-04-23

申请号：US14254537

申请日：2014-04-16

Applicant: Samsung Display Co., Ltd.

Inventor： Byeong-Jin LEE ,  Joo-Han BAE ,  Byeongkyu JEON ,  Sungku KANG ,  Jinhwan KIM ,  Heewoong PARK ,  Jee-Hun LIM

IPC: H03K17/96 ,  G06F3/0354 ,  G06F3/044

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06F2203/04111 ,  G06F2203/04112 ,  H03K2217/96075 ,  H03K2217/960755

Abstract: A touch screen panel includes a touch substrate, first sensing electrodes, second sensing electrodes, and outer lines. The touch substrate includes a touch active area and a touch non-active area. The first and second sensing electrodes are disposed in the touch active area and insulated from each other while crossing each other. Each first sensing electrode includes a first sensing metal layer and a first transparent sensing electrode layer. Each second sensing electrode includes a second sensing metal layer and a second transparent sensing electrode layer. Each outer line includes a first outer metal layer, a transparent outer electrode layer, and a second outer metal layer.

Abstract translation: 触摸屏面板包括触摸基板，第一感测电极，第二感测电极和外线。 触摸基板包括触摸有源区域和触摸非有源区域。 第一感测电极和第二感测电极设置在触摸有源区域中并彼此绝缘。 每个第一感测电极包括第一感测金属层和第一透明感测电极层。 每个第二感测电极包括第二感测金属层和第二透明感测电极层。 每个外线包括第一外金属层，透明外电极层和第二外金属层。

公开(公告)号：US20140225195A1

公开(公告)日：2014-08-14

申请号：US13914821

申请日：2013-06-11

Applicant: Samsung Display Co., LTD.

Inventor： Gun-Hee KIM ,  Sei-Yong PARK ,  Woo-Ho JEONG ,  Jin-Hyun PARK ,  Jee-Hun LIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.

Abstract translation: 薄膜晶体管基板包括基板，设置在基板上的栅极电极，设置在栅电极上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体图案，其中氧化物半导体图案包括第一区域，其载流子浓度 在约1017每立方厘米至约1019每立方厘米的范围内，第二区域的载流子浓度小于第一区域的载流子浓度，蚀刻停止器设置在氧化物半导体图案上，其中蚀刻停止器覆盖 氧化物半导体图案的第一区域和第二区域，与蚀刻停止器和第二区域部分重叠的信号电极，以及覆盖蚀刻停止器和信号电极的钝化层。

公开(公告)号：US20140291665A1

公开(公告)日：2014-10-02

申请号：US14180171

申请日：2014-02-13

Applicant: Samsung Display Co., Ltd.

Inventor： Gun Hee KIM ,  Jin Hyun PARK ,  Kyoung Won LEE ,  Byung Du AHN ,  Jee-Hun LIM ,  Jun Hyung LIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.

Abstract translation: 薄膜晶体管阵列面板包括：设置在基板上的栅极电极，设置在栅电极上的绝缘层，设置在栅极绝缘层上的氧化物半导体，与氧化物半导体的一部分重叠的源电极，与另一个重叠的漏电极 部分氧化物半导体; 以及设置在氧化物半导体和源电极之间以及氧化物半导体和漏电极之间的缓冲层。 缓冲层包含锡作为掺杂材料。 掺杂材料的重量百分比大于约0％且小于或等于约20％。