公开(公告)号：US20230170441A1

公开(公告)日：2023-06-01

申请号：US17997519

申请日：2021-04-23

Applicant: Samsung Display Co., LTD.

Inventor： Mi Hyang SHEEN ,  Sang Hyung LIM ,  Myeong Kyu PARK ,  Na Ri AHN ,  Doo Hyoung LEE

IPC: H01L33/38 ,  H01L33/24 ,  H01L33/60 ,  H01L33/62 ,  H01L25/075

CPC classification number: H01L33/382 ,  H01L25/0753 ,  H01L33/24 ,  H01L33/60 ,  H01L33/62

Abstract: Provided are a light emitting device and a display apparatus comprising the same. The light emitting device comprises a light emitting device core extending in one direction, and a transmission filter layer surrounding a part of the side surface of the light emitting device core, wherein the side surface of the light emitting device core comprises a first area having the transmission filter layer arranged therein, and a second area not having the transmission filter layer arranged therein.

公开(公告)号：US20210296422A1

公开(公告)日：2021-09-23

申请号：US17089246

申请日：2020-11-04

Applicant: Samsung Display Co., LTD.

Inventor： Sang Hyung LIM ,  Jee Hoon KIM ,  Mi Hyang SHEEN ,  Jin Ho JANG ,  Myeong Kyu PARK ,  Na Ri AHN ,  Hui Won YANG ,  Doo Hyoung LEE

IPC: H01L27/32 ,  H01L51/52

Abstract: A display device includes a first conductive pattern on a substrate, a first insulating layer on the first conductive pattern, a semiconductor pattern on the first insulating layer, a second insulating layer on the first insulating layer and the semiconductor pattern, and a second conductive pattern on the second insulating layer. A first edge of the first conductive pattern faces a second edge of the second conductive pattern, the first conductive pattern does not overlap the second conductive pattern in an area where the first edge faces the second edge, the semiconductor pattern is in the area where the first edge faces the second edge, the second conductive pattern overlaps the second insulating layer, and the second insulating layer includes a third edge protruding from the second edge of the second conductive pattern.

公开(公告)号：US20130328042A1

公开(公告)日：2013-12-12

申请号：US13679910

申请日：2012-11-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung LEE ,  Chan Woo YANG ,  Seung-Ho JUNG ,  Doo Na KIM ,  Bo Sung KIM ,  Eun Hye PARK ,  June Whan CHOI

IPC: H01L29/786 ,  H01B1/06 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio (R, R[mol %]=[In]/[In+Zn+Sn]/100) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, R[mol %]=[In]/[In+Zn+Sn]/100) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），并且铟的摩尔比（R，R [mol％] = [In] / [In + Zn + Sn] / 100） （In）/ [In + Zn + Sn] / 100）的摩尔比（R，R [mol％] = [In] / [In + Zn + Sn] / 100）小于约20％ In）的半导体层中的金属为约5％至约13％。

公开(公告)号：US20130320327A1

公开(公告)日：2013-12-05

申请号：US13673195

申请日：2012-11-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung LEE ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.