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公开(公告)号：US20170162709A1
公开(公告)日：2017-06-08
申请号：US15327615
申请日：2014-11-07
发明人： Nobutake Nodera , Shigeru Ishida , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L29/786 , G02F1/1362
CPC分类号： H01L29/78663 , G02F1/136277 , G02F1/1368 , G02F2001/136295 , H01L29/66765 , H01L29/78696
摘要： The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
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公开(公告)号：US10310347B2
公开(公告)日：2019-06-04
申请号：US15917006
申请日：2018-03-09
发明人： Shigeru Ishida , Nobutake Nodera , Ryouhei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L27/12 , G02F1/1368 , G02F1/1362 , H01L29/49 , H01L29/786 , G02F1/1345
摘要： There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
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公开(公告)号：US10243003B2
公开(公告)日：2019-03-26
申请号：US15327588
申请日：2015-03-27
发明人： Nobutake Nodera , Shigeru Ishida , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
摘要： The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.
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公开(公告)号：US10038098B2
公开(公告)日：2018-07-31
申请号：US15327615
申请日：2014-11-07
发明人： Nobutake Nodera , Shigeru Ishida , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L29/786 , G02F1/1362
CPC分类号： H01L29/78663 , G02F1/136277 , G02F1/1368 , G02F2001/136295 , H01L29/66765 , H01L29/78696
摘要： The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
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公开(公告)号：US20180196294A1
公开(公告)日：2018-07-12
申请号：US15917006
申请日：2018-03-09
发明人： Shigeru Ishida , Nobutake Nodera , Ryouhei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： G02F1/1368 , H01L27/12 , G02F1/1362 , H01L29/49 , H01L29/786
CPC分类号： G02F1/1368 , G02F1/13454 , G02F1/136227 , G02F1/136286 , G02F2201/123 , G02F2202/103 , H01L27/124 , H01L27/1288 , H01L29/4908 , H01L29/78672
摘要： There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
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公开(公告)号：US20170154901A1
公开(公告)日：2017-06-01
申请号：US15327588
申请日：2015-03-27
发明人： Nobutake Nodera , Shigeru Ishida , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L27/1222 , H01L29/66765 , H01L29/7866 , H01L29/78669 , H01L29/78696
摘要： The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.
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公开(公告)号：US10008606B2
公开(公告)日：2018-06-26
申请号：US15561686
申请日：2015-03-30
发明人： Shigeru Ishida , Nobutake Nodera , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L29/786
CPC分类号： H01L29/78663 , H01L29/78609 , H01L29/78669 , H01L29/78672 , H01L29/78678 , H01L29/78696
摘要： The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
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公开(公告)号：US20180097120A1
公开(公告)日：2018-04-05
申请号：US15561686
申请日：2015-03-30
发明人： Shigeru Ishida , Nobutake Nodera , Ryohei Takakura , Yoshiaki Matsushima , Takao Matsumoto , Kazuki Kobayashi , Taimi Oketani
IPC分类号： H01L29/786
CPC分类号： H01L29/78663 , H01L29/786 , H01L29/78669 , H01L29/78672 , H01L29/78678
摘要： The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
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