公开(公告)号：US11620077B2

公开(公告)日：2023-04-04

申请号：US17224747

申请日：2021-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F3/06 ,  G06F13/42

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

公开(公告)号：US20220350764A1

公开(公告)日：2022-11-03

申请号：US17811209

申请日：2022-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

公开(公告)号：US20220012199A1

公开(公告)日：2022-01-13

申请号：US17339083

申请日：2021-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G06F13/28 ,  G06F13/372 ,  G06F13/37 ,  G06F17/14 ,  G06F9/46

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

公开(公告)号：US20210342091A1

公开(公告)日：2021-11-04

申请号：US17224747

申请日：2021-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F3/06 ,  G06F13/42

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

公开(公告)号：US11940492B2

公开(公告)日：2024-03-26

申请号：US17656538

申请日：2022-03-25

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

CPC classification number: G01R31/31813 ,  G01R31/318307 ,  G01R31/318385 ,  G01R31/318536 ,  G01R31/318547 ,  G01R31/3187

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.

公开(公告)号：US20220317186A1

公开(公告)日：2022-10-06

申请号：US17656538

申请日：2022-03-25

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G01R31/3181 ,  G01R31/3183 ,  G01R31/3185

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.

公开(公告)号：US11354257B2

公开(公告)日：2022-06-07

申请号：US17224772

申请日：2021-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F17/16 ,  G06F13/16 ,  G06F7/50 ,  G06F7/523 ,  G06F13/28 ,  G06F13/40

Abstract: An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

公开(公告)号：US20210342277A1

公开(公告)日：2021-11-04

申请号：US17224772

申请日：2021-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F13/16 ,  G06F7/523 ,  G06F7/50 ,  G06F13/40 ,  G06F13/28

Abstract: An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

公开(公告)号：US11675720B2

公开(公告)日：2023-06-13

申请号：US17811209

申请日：2022-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

CPC classification number: G06F13/287 ,  G06F9/467 ,  G06F13/37 ,  G06F13/372 ,  G06F17/142

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

公开(公告)号：US11461257B2

公开(公告)日：2022-10-04

申请号：US17339083

申请日：2021-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.